u-boot.git/drivers/clk/qcom, branch v2025.04

clk: qcom: x1e80100: add support for PCIe clocks

2025-01-22T15:36:16Z

Add the PCIe clocks for the x1e80100 GCC. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20241125-topic-pcie-clk-v1-4-4315d1e4e164@linaro.org Signed-off-by: Caleb Connolly

clk: qcom: sm8650: add support for PCIe clocks

2025-01-22T15:36:16Z

Add the PCIe clocks for the SM8650 GCC. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20241125-topic-pcie-clk-v1-3-4315d1e4e164@linaro.org Signed-off-by: Caleb Connolly

clk: qcom: sm8550: add support for PCIe clocks

2025-01-22T15:36:16Z

Add the PCIe clocks for the SM8550 GCC. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20241125-topic-pcie-clk-v1-2-4315d1e4e164@linaro.org Signed-off-by: Caleb Connolly

clk: qcom: add clk_phy_mux_enable() for PCIe PIPE clock

2025-01-22T15:36:15Z

The PCIe PIPE clock requires a special setup function to mux & enable the clock from the PCIe PHY before the PHY has enabled the clock. Import the clk_phy_mux_enable() from the Linux driver to use the same implementation regarding the PIPE clock. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20241125-topic-pcie-clk-v1-1-4315d1e4e164@linaro.org Signed-off-by: Caleb Connolly

clk: qcom: Add X1E80100 clock driver

2025-01-22T15:34:26Z

Add Clock driver for the GCC block found in the X1E80100 SoC. Signed-off-by: Neil Armstrong Reviewed-by: Caleb Connolly Tested-by: Caleb Connolly # Yoga Slim 7x Link: https://lore.kernel.org/r/20241118-topic-x1e80100-clk-v1-1-8841e87ad81f@linaro.org Signed-off-by: Caleb Connolly

clk/qcom: add initial clock driver for qcs9100

2025-01-22T15:26:51Z

Add initial set of clocks and resets for enabling U-Boot on QCS9100 based Ride platforms. Reviewed-by: Neil Armstrong Signed-off-by: Varadarajan Narayanan Link: https://lore.kernel.org/r/20250110050817.3819282-4-quic_varada@quicinc.com Signed-off-by: Caleb Connolly

clk/qcom: sm8250: add debug data

2024-10-04T12:57:04Z

Drop in the RCG and GPLL data for debugging these clocks. Signed-off-by: Caleb Connolly

clk/qcom: sm6115: add debug data

2024-10-04T12:57:04Z

Add "clk dump" support for SM6115. Signed-off-by: Caleb Connolly

clk/qcom: sdm845: add dump data

2024-10-04T12:57:03Z

Add debug data to dump PLL and RCG clocks. Signed-off-by: Caleb Connolly

clk/qcom: implement clk dump

2024-10-04T12:57:03Z

Add support for dumping a few of the clocks used on Qualcomm platforms. Naming the Global PLL's, Root Clock Generators, and gate clocks. This helps a lot with platform bringup and feature enablement by making it easy to sanity check that the clocks are programmed correctly. == Usage == Enable CONFIG_CMD_CLK and "#define LOG_DEBUG" at the top of qcom-.c. The "clk dump" command should print the states of all the gates, GPLLs and RCGs for your SoC. == Glossary == RCG: Root Clock Generator * Takes in some fairly arbitrary high freq clock (configurable clock source and options for taking just even pulses and other things) * Output frequency = input_freq * (m/n) * (1/d) where m/n are arbitrary 8 or 16-bit values (depending on the RCG), and d is a number (with support for .5 offsets). GPLL: Global Phase Locked Loop * Crystal as input * integer multiplier + exponent part (2^-40) Gate: Simple on/off clock * Put between RCGs and the peripherals they power * Required to allow for correct power sequencing If you do the maths manually using the equations from "clk dump", the numbers should roughly line up by they're likely to be out by a handful of MHz. They output is formatted so that it can be pasted directly into the python interpreter. Signed-off-by: Caleb Connolly