u-boot.git/drivers/clk/qcom, branch v2026.07

clk/qcom: milos: Add TCSRCC clocks

2026-06-30T11:04:59Z

With a recent change to the UFS driver, now all clocks need to be available. Add all the clocks from the TCSRCC block on Milos. Signed-off-by: Luca Weiss Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260625-milos-ufs-fix-v1-2-b0923dabc35f@fairphone.com Signed-off-by: Casey Connolly

clk/qcom: milos: Add remaining UFS clocks

2026-06-30T11:04:59Z

With a recent change to the UFS driver, now all clocks need to be available. Add them. Signed-off-by: Luca Weiss Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260625-milos-ufs-fix-v1-1-b0923dabc35f@fairphone.com Signed-off-by: Casey Connolly

clk/qcom: Add Milos clock driver

2026-04-27T10:38:44Z

Add Clock driver for the GCC block found in the Milos SoC. The qcom-snps-eusb2-hsphy driver requires the TCXO frequency ("ref" clock), so we need to pass that as well. Signed-off-by: Luca Weiss Reviewed-by: Sumit Garg Link: https://patch.msgid.link/20260318-milos-bringup-v2-2-650b91dd75d8@fairphone.com Signed-off-by: Casey Connolly

clk: qcom: sc7280: add missing SDCC1 clocks

2026-04-27T10:38:44Z

Add GCC_SDCC1_AHB_CLK and GCC_SDCC1_APPS_CLK gate clocks. Required on platforms where SDCC1 is used for eMMC. Link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit?id=a3cc092196ef63570c8744c3ac88c3c6c67ab44b Signed-off-by: Ajit Singh Reviewed-by: Casey Connolly Reviewed-by: Sumit Garg Link: https://patch.msgid.link/20260226193217.82657-1-blfizzyy@gmail.com Signed-off-by: Casey Connolly

drivers: clk: qcom: sc7280: Add USB3 PHY pipe clock

2026-04-27T10:33:30Z

Add support for GCC_USB3_PRIM_PHY_PIPE_CLK which is required by the USB3 PHY on SC7280/QCM6490 platforms. Signed-off-by: Balaji Selvanathan Reviewed-by: Neil Armstrong Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20251203110735.1959862-2-balaji.selvanathan@oss.qualcomm.com Signed-off-by: Casey Connolly

clk: qcom: qcs615: Add GCC_AHB2PHY_WEST_CLK clock support

2026-03-24T10:34:58Z

Add GCC_AHB2PHY_WEST_CLK gate clock definition to the QCS615 clock driver. This clock is required for proper PHY operation and eliminates clock-related warnings during USB initialization. Signed-off-by: Balaji Selvanathan Reviewed-by: Sumit Garg Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260213-talos_usb-v1-2-4c4355d61437@oss.qualcomm.com Signed-off-by: Casey Connolly

clk: qcom: qcs615: Add GCC_USB3_PRIM_CLKREF_CLK support

2026-03-24T10:34:58Z

Add support for GCC_USB3_PRIM_CLKREF_CLK to the QCS615 clock driver. This clock is referenced in the device tree USB node but was not implemented in U-Boot, causing "Clock 152 not found" warnings during fastboot run. Signed-off-by: Balaji Selvanathan Reviewed-by: Sumit Garg Link: https://patch.msgid.link/20260213-talos_usb-v1-1-4c4355d61437@oss.qualcomm.com Signed-off-by: Casey Connolly

clk: qcom: sa8775p: Fix USB clock configuration and add resets

2026-01-14T15:25:09Z

Correct USB30 primary clock RCG configuration and add missing USB3_PRIM_PHY_AUX_CMD_RCGR RCG configuration. Above taken from Linux commit 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p") Add missing USB3_PRIM_PHY_PIPE_CLK gate clock definition. Extend reset map with USB-related BCR entries and video BCR for comprehensive reset control support. Signed-off-by: Balaji Selvanathan Link: https://patch.msgid.link/20260113065856.3287772-1-balaji.selvanathan@oss.qualcomm.com [casey: indentation fix] Signed-off-by: Casey Connolly

clk: qcom: sa8775p: Add QUP serial engine clock support

2026-01-14T15:25:09Z

Add clock gate definitions and entries for QUP (Qualcomm Universal Peripheral) serial engine clocks across all four wrappers on SA8775P. This enables proper clock management for I2C, SPI, and UART peripherals connected to the QUP blocks. This resolves the "unknown clock ID 133" error for UART10 and provides complete QUP clock infrastructure for the platform. Signed-off-by: Swathi Tamilselvan Signed-off-by: Balaji Selvanathan Link: https://patch.msgid.link/20260113042213.3107106-1-balaji.selvanathan@oss.qualcomm.com Signed-off-by: Casey Connolly

clk/qcom: sc7280: add more QUP clocks

2026-01-14T15:25:09Z

Add more clocks for UART2, i2c9 and a few others. This is enough to get the rubikpi 3 working. Link: https://patch.msgid.link/20260108195007.3156604-1-casey.connolly@linaro.org Signed-off-by: Casey Connolly