u-boot.git/drivers/clk/renesas, branch master

clk: renesas: Do not disable realtime modules on R8A77995 D3

2025-12-29T19:47:53+00:00

Later versions of the datasheet makes it clear D3 do not have any
realtime module stop control registers (RMSTPCRx). Remove the
manipulation of them from the module clock table to match this.

Suggested-by: Marek Vasut 
Signed-off-by: Niklas Söderlund

clk: renesas: Do not enable MSTP4 extra modules on R8A77995 D3

2025-12-29T19:47:53+00:00

Since commit a2bd99549c61 ("clk: renesas: Tear clock controller down
last before booting OS") enabling the module gated by bit 8 in MSTP4
prevents Linux from booting. The bits 8 and 7 of MSTP4 where only
documented in early versions of the datasheet and have since been
removed.

To allow Linux to boot update the MSTP4 enable value to reflect the
hardware default, 0x80.

Suggested-by: Marek Vasut 
Signed-off-by: Niklas Söderlund

clk: renesas: Introduce temporary compound clock for SCP compatibility

2025-12-02T23:17:15+00:00

The current state of SCP on Renesas R-Car Gen5 is not yet final and
is still missing full clock control, the clock control is exposed as
separate enable/disable and rate controls.

Temporarily introduce custom local compound clock, which are used as
an adaptation layer between U-Boot clock tree and current state of
SCP, and which bind two SCP clock into a single compound clock, which
provides both enable/disable and rate controls.

This is mainly meant to be used by SD/eMMC controller, to allow the
driver to both turn its clock on and off, and also obtain the current
clock rate. This is going to be removed once the SCP clock protocol
solidifies.

Signed-off-by: Marek Vasut

clk: renesas: Isolate R-Car Gen3 driver to Gen3, Gen4 and RZ/G2L

2025-11-07T16:40:42+00:00

Isolate Renesas R-Car Gen3 clock driver to R-Car Gen3 and Gen4 and RZ/G2L.
The Renesas R-Car Gen5 uses SCMI clock protocol driver instead. This is
a preparatory change for R-Car Gen5. No functional change.

Signed-off-by: Marek Vasut

clk: renesas: Do not test unsigned variable to be less than 0

2025-08-06T14:52:27+00:00

In rcar_clk_set_rate64_div_table the unsigned variable 'value' is used
to receive the return value from rcar_clk_get_table_val which returns an
int and then attempts to test for being less than 0, which can never be
true. Instead declare value as an int so the code can behave as
expected. Also remove initial values from 'value' and 'div' as they are
not needed.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody 
Reviewed-by: Marek Vasut

clk: renesas: Handle CLK_TYPE_GEN4_MDSEL in gen3_clk_get_rate64()

2025-06-18T13:08:52+00:00

Add support of CLK_TYPE_GEN4_MDSEL clock type to gen3_clk_get_rate64()
function. In particular, this type of clock is used by Renesas R-Car
Gen4 watchdog. It operates similarly to CLK_TYPE_GEN3_MDSEL clock.

Signed-off-by: Shmuel Leib Melamud 
Reviewed-by: Mattijs Korpershoek 
Reviewed-by: Marek Vasut 
Reviewed-by: Stefan Roese

drivers: use lowercase hex prefix style

2025-06-14T15:09:39+00:00

Use consistent lowercase hex prefix style in drivers/*

Does not change hex prefix case in allcaps uppercase style error messages

Signed-off-by: E Shattow

clk: rzg2l: Ignore disable for core clocks

2025-03-11T22:06:18+00:00

Following on from commit 9a699a0a0d62 ("clk: rzg2l: Ignore enable for
core clocks"), we also need to ignore attempts to disable core clocks to
avoid the need for conditionals around clk_disable_bulk() calls in
drivers which support both RZ/G2L and other Renesas SoCs.

Signed-off-by: Paul Barker 
Reviewed-by: Marek Vasut

clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks

2024-12-20T21:20:37+00:00

Early revisions of the R-Car V4M Series Hardware User’s Manual
contained an incorrect formula for the CPU core clocks:

    ZCnφ = (PLL2VCO x 1/2) x mult/32

Dang-san fixed this by using CLK_PLL2_DIV2 instead of CLK_PLL2 as the
parent clock.

In Rev.0.70 of the documentation, the formula was corrected to:

    ZCnφ = (PLL2VCO x 1/4) x mult/32

As the CPG Block Diagram now shows a separate 1/4 post-divider for PLL2,
the use of CLK_PLL2_DIV2 is a recurring source of confusion.  Hence get
rid of CLK_PLL2_DIV2, and include the proper 1/4 post-divider in the
invocation of the DEF_GEN4_Z() macro, like is done on other R-Car Gen4
(and Gen3) SoCs.

Ported from Linux commit
92850bed9d4d ("clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks")

Reported-by: Vinh Nguyen 
Signed-off-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/0d2789cac2bf306145fe0bbf269c2da5942bb68f.1728377724.git.geert+renesas@glider.be
Signed-off-by: Marek Vasut

clk: renesas: Fix R-Car spelling

2024-12-11T07:36:24+00:00

The correct spelling is R-Car, including the dash, update the usage.
Kconfig strings and comment changes only, no functional change.

Signed-off-by: Marek Vasut