u-boot.git/drivers/clk/rockchip/Makefile, branch master

clk: rockchip: Add support for RK3506

2026-03-10T16:07:03+00:00

Add clock driver for RK3506.

Imported from vendor U-Boot linux-6.1-stan-rkr6 tag with minor
adjustments and fixes for mainline.

Signed-off-by: Finley Xiao 
Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang

clk: rockchip: Add rk3576 clk support

2025-04-23T14:12:05+00:00

Add clock driver support for Rockchip RK3576 SoC.

Signed-off-by: Elaine Zhang 
[adapted to mainline u-boot]
Signed-off-by: Heiko Stuebner 
Reviewed-by: Jonas Karlman 
Reviewed-by: Kever Yang

clk: rockchip: Add support for RK3528

2025-04-23T14:12:04+00:00

Add clock driver for RK3528.

Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with minor
adjustments and fixes for mainline.

Signed-off-by: Joseph Chen 
Signed-off-by: Finley Xiao 
Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang

clk: rockchip: Add rk3588 clk support

2023-02-28T10:07:27+00:00

Add clock driver support for Rockchip RK3588 SoC.

Signed-off-by: Elaine Zhang 
Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
Signed-off-by: Kever Yang

clk: rockchip: Add rv1126 clk support

2023-01-16T10:01:11+00:00

Add clock driver support for Rockchip RV1126 SoC.

Signed-off-by: Joseph Chen 
Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang

rockchip: rk3066: add clock driver for rk3066 soc

2022-04-18T03:25:13+00:00

Add the clock driver for the rk3066 platform.

Derived from the rk3288 and rk3188 driver it
supports only a bare minimum to bring up the system
to reduce the TPL size for:
  SDRAM clock configuration.
  The boot devices NAND, EMMC, SDMMC, SPI.
  A UART for the debug messages (fixed) at 115200n8.
  A SARADC for the recovery button.
  A TIMER for the delays (fixed).

There's support for two possible frequencies,
the safe 600MHz which will work with default pmic settings and
will be set to get away from the 24MHz default and
the maximum of 1.416Ghz, which boards can set if they
were able to get pmic support for it.

After the clock tree is set during the TPL probe
there's no parent update support.

In OF_REAL mode the drivers ns16550.c and dw-apb-timer.c
obtain the (fixed) clk_get_rate from the clock driver
instead of platdata.

The rk3066 cru node has a number of assigned-clocks properties
that call the .set_rate() function. Add them to the list so that
they return a 0 instead of -ENOENT.

Signed-off-by: Paweł Jarosz 
Signed-off-by: Johan Jonker 
Reviewed-by: Sean Anderson 
Reviewed-by: Kever Yang

rockchip: rk3568: add clock driver

2021-06-18T06:36:06+00:00

Add rk3568 clock driver and cru structure definition.

Signed-off-by: Elaine Zhang 
Reviewed-by: Kever Yang

rockchip: clk: Add clk driver for rk3308

2019-11-17T09:22:53+00:00

Add clk controller driver for RK3308 SOC.

This patch depends on Elaine's pll patch[0].

[0]http://patchwork.ozlabs.org/patch/1183718/

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang

rockchip: clk: pll: add common pll setting funcs

2019-11-17T09:22:53+00:00

Common PLL setup function, compatible with different SOC.
Mainly for the subsequent new SOC use.

Signed-off-by: Elaine Zhang 
Reviewed-by: Kever Yang

rockchip: clk: add px30 clock driver

2019-11-17T09:23:07+00:00

The px30 contains 2 separate clock controllers, pmucru and cru.
Add drivers for them.

Signed-off-by: Kever Yang 
Signed-off-by: Heiko Stuebner 
Reviewed-by: Kever Yang