u-boot.git/drivers/clk/rockchip, branch next

clk: rockchip: pll: fix overflow and drop manual two's complement on RK3588/RK3576

2026-08-12T14:55:03Z

The TRM defines the fractional PLL adjustment coefficient as a signed two's complement number, 16 bits wide, so store and use it as such to avoid confusion and enable proper signed arithmetics, promoting operands with automatic sign extension. This also fixes an overflow when the current rk3588_pll_get_rate calculates the fractional component in 32 bits before assigning it to a 64-bit holding variable, given that OSC_HZ is 24000000U and k can be from -32768 to 32767. Fixes: b851c006a150 ("clk: rockchip: pll: Add pll_rk3588 type for rk3588") Reviewed-by: Quentin Schulz Signed-off-by: Alexey Charkov Link: https://patch.msgid.link/20260723-rk3588-fracpll-v2-5-382d113f3a80@flipper.net Signed-off-by: Quentin Schulz

clk: rockchip: pll: let rockchip_rk3588_pll_k_get update m directly

2026-08-12T14:54:58Z

Selecting the next integer multiplier m is coupled to setting a negative fractional coefficient k. The current code checks for negative k in two separate places, which is error-prone. Let rockchip_rk3588_pll_k_get update m directly, to make it the single source of truth for the final value of the integer multiplier m, which also reduces the number of scattered conditional branches in the code. Signed-off-by: Alexey Charkov Reviewed-by: Quentin Schulz Link: https://patch.msgid.link/20260723-rk3588-fracpll-v2-4-382d113f3a80@flipper.net Signed-off-by: Quentin Schulz

clk: rockchip: pll: fix RK3588 frac PLL result for k=-32768

2026-08-12T14:54:38Z

Current code needlessly sets the k value to 0 when it is calculated as -32768, which is a valid value for the RK3588 frac PLL. This results in the PLL output frequency being higher than requested when the requested frequency is exactly halfway between two integer-multiplier PLL output frequencies. Negative values of k cannot be greater than 32768 in magnitude either, because that case has been handled just above the enclosing if statement, so the check for k > 32767 is redundant. Fixes: 6bfb37e70209 ("clk: rockchip: rk3588: fix up the frac pll calculation") Signed-off-by: Alexey Charkov Reviewed-by: Quentin Schulz Link: https://patch.msgid.link/20260723-rk3588-fracpll-v2-3-382d113f3a80@flipper.net Signed-off-by: Quentin Schulz

clk: rockchip: pll: fix rounding of negative k in RK3588 frac PLL

2026-08-12T14:50:43Z

Current code uses magical constants when rounding up the magnitude of negative fractional PLL component k. This leads to overshooting the requested rate when the calculated fractional part has less than 0.3 in its decimal part due to failure to round up the fractional part. Use a proper rounding up function to avoid overshooting the requested rate and make the calculation more readable. Fixes: 6bfb37e70209 ("clk: rockchip: rk3588: fix up the frac pll calculation") Reviewed-by: Quentin Schulz Signed-off-by: Alexey Charkov Link: https://patch.msgid.link/20260723-rk3588-fracpll-v2-2-382d113f3a80@flipper.net Signed-off-by: Quentin Schulz

clk: rockchip: pll: drop misleading fout in rockchip_rk3588_pll_k_get()

2026-08-12T14:50:43Z

The calculation in rockchip_rk3588_pll_k_get() uses an intermediate variable misleadingly named fout, which is not the output frequency. Drop it and inline its calculation into the k assignment, which also improves clarity. While at that, also drop the redundant reassignment of fref which doesn't change within this function. Reviewed-by: Quentin Schulz Signed-off-by: Alexey Charkov Link: https://patch.msgid.link/20260723-rk3588-fracpll-v2-1-382d113f3a80@flipper.net Signed-off-by: Quentin Schulz

rockchip: clk: clk_rk3576: Add support for RK3576 GMAC 25MHz clock output

2026-06-09T16:19:05Z

Rockchip RK3576 SoC has two built-in GMACs which connect to external PHYs via RGMII interface. The RGMII link can be clocked by either the PHY or the SoC. When the SoC is the master, as is the case on the RK3576 EVB1, the output clock needs to be configured in the CRU. Add the respective logic for getting and setting the RGMII reference clock output for both GMAC0 and GMAC1. Signed-off-by: Alexey Charkov Reviewed-by: Quentin Schulz Reviewed-by: Kever Yang

clk: rockchip: rk3576: Add CLK_REF_USB3OTGx support

2026-06-08T13:21:52Z

The CLK_REF_USB3OTGx clocks are used as reference clocks for the two DWC3 blocks. Add simple support to get rate of CLK_REF_USB3OTGx clocks to fix reference clock period configuration. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang

clk: rockchip: rk3528: Add CLK_REF_USB3OTG support

2026-06-08T13:21:52Z

The CLK_REF_USB3OTG clock is used as reference clock for the DWC3 block. Add simple support to get rate of CLK_REF_USB3OTG clock to fix reference clock period configuration. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang

Merge tag 'u-boot-rockchip-20260309' of https://source.denx.de/u-boot/custodians/u-boot-rockchip into next

2026-03-10T16:07:04Z

CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/29452 - New SoC support: RK3506, RK3582; - New Board support: RK3528 FriendlyElec NanoPi Zero2; - Other fixes

clk: rockchip: Add support for RK3506

2026-03-10T16:07:03Z

Add clock driver for RK3506. Imported from vendor U-Boot linux-6.1-stan-rkr6 tag with minor adjustments and fixes for mainline. Signed-off-by: Finley Xiao Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang