u-boot.git/drivers/clk/rockchip, branch v2017.05

rockchip: clk: rk3399: 24MHz is not a power of 2

2017-04-05T02:01:57Z

The clock driver for the RK3399 mistakenly used (24 * 2^20) where it should have used (24 * 10^6) in a few calculations. This commits fixes this. Signed-off-by: Philipp Tomsich Acked-by: Simon Glass

rockchip: clk: rk3399: add clocking support for Ethernet

2017-04-05T02:01:57Z

The Ethernet driver for the RK3288/3399 GMAC makes sure that the clock is ungated through a call to clk_set_rate(...). Even though nothing needs to be done on the RK3399 (the clock gates are open and the clock is external), we need to implement enough support to at least return success to enable driver probing. X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich Acked-by: Simon Glass

rockchip: clk: rk3399: fix warnings for unused variables in SPL/non-SPL

2017-04-05T02:01:57Z

Due to differences in the code paths for SPL and non-SPL, some static constant structures remain unused in each build variant. This raises warnings with recent GCC versions (we currently use GCC-6.3). The warnings addressed in this commit (by matching #if conditions for the variable definition with their uses) are: * for the SPL build: drivers/clk/rockchip/clk_rk3399.c:53:29: warning: 'cpll_init_cfg' defined but not used [-Wunused-const-variable=] static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); ^~~~~~~~~~~~~ drivers/clk/rockchip/clk_rk3399.c:52:29: warning: 'gpll_init_cfg' defined but not used [-Wunused-const-variable=] static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); ^~~~~~~~~~~~~ * for the non-SPL build: drivers/clk/rockchip/clk_rk3399.c:54:29: warning: 'ppll_init_cfg' defined but not used [-Wunused-const-variable=] static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); ^~~~~~~~~~~~~ Signed-off-by: Philipp Tomsich Acked-by: Simon Glass

rockchip: clk: rk3188: Allow configuration of the armclk

2017-04-05T02:01:57Z

The armclk starts in slow mode (24MHz) on the rk3188, which makes the whole startup take a lot of time. We therefore want to at least move to the safe 600MHz value we can use with default pmic settings. This is also the freqency the proprietary sdram-init leaves the cpu at. For boards that have pmic control later in u-boot, we also add the option to set the maximum frequency of 1.6GHz, if they so desire. Signed-off-by: Heiko Stuebner Acked-by: Simon Glass

rockchip: rk3328: add clock driver

2017-03-16T22:03:46Z

Add rk3328 clock driver and cru structure definition. Signed-off-by: William Zhang Signed-off-by: Kever Yang

rockchip: rk3188: Add clock driver

2017-03-16T22:03:45Z

Add a driver for setting up and modifying the various PLLs and peripheral clocks on the RK3188. Signed-off-by: Heiko Stuebner Reviewed-by: Simon Glass Tested-by: Kever Yang

rockchip: clk: rk3288: limit gpll and cpll init to SPL build

2017-03-16T22:03:44Z

The gpll and cpll init values are only used in rk_clk_init in the SPL and therefore produce compile time warnings in regular uboot builds. Fix that with an #ifdef. Signed-off-by: Heiko Stuebner Acked-by: Simon Glass Added rockchip tag: Signed-off-by: Simon Glass

rockchip: clk: rk3399: update driver for spl

2017-03-16T22:03:43Z

Add ddr clock setting, add rockchip_get_pmucru API, and enable of-platdata support. Signed-off-by: Kever Yang Reviewed-by: Simon Glass Added rockchip tag and fix pmuclk_init() build warning: Signed-off-by: Simon Glass

rockchip: clk: Support setting ACLK

2016-11-26T00:59:31Z

Add basic support for setting the ARM clock, since this allows us to run at maximum speed in U-Boot. Currently only a single speed is supported (1.8GHz). Signed-off-by: Simon Glass

rockchip: rk3288: Move rockchip_get_cru() out of the driver

2016-10-30T19:29:06Z

This function is called from outside the driver. It should be placed into common SoC code. Move it. Signed-off-by: Simon Glass Reviewed-by: Kever Yang