u-boot.git/drivers/clk/sifive/Makefile, branch master

clk: sifive: only build sifive-prci.o for CONFIG_CLK_SIFIVE_PRCI

2023-07-06T09:28:08+00:00

If we're building non FU540/FU740 SoC drivers, then the sifive-prci.o
is not needed. Only build this when CONFIG_CLK_SIFIVE_PRCI is selected.

Signed-off-by: Ben Dooks 
Reviewed-by: Leo Yu-Chi Liang

drivers: clk: add fu740 support

2021-05-31T08:35:54+00:00

Add fu740 support. One abstract layer is added for supporting
multiple chips such as fu540 and fu740.

Signed-off-by: Green Wan

clk: sifive: Drop GEMGXL clock driver

2019-07-19T06:24:51+00:00

The GEMGXL clock driver is now directly part of Cadence MACB
ethernet driver in upstream Linux kernel. There is no separate
GEMGXL clock driver in upstream Linux kernel hence we drop
GEMGXL clock driver from U-Boot as well.

Signed-off-by: Anup Patel 
Reviewed-by: Bin Meng

clk: sifive: Factor-out PLL library as separate module

2019-07-19T06:24:51+00:00

To match SiFive clock driver with latest Linux, we factor-out PLL
library as separate module under drivers/clk/analogbits.

Signed-off-by: Anup Patel 
Reviewed-by: Bin Meng

clk: sifive: Add clock driver for GEMGXL MGMT

2019-06-01T18:33:17+00:00

This adds a clock driver to support the GEMGXL management IP block
found in FU540 SoCs to control GEM TX clock operation mode for
10/100/1000 Mbps.

Signed-off-by: Bin Meng 
Reviewed-by: Lukas Auer 
Tested-by: Lukas Auer

clk: Add SiFive FU540 PRCI clock driver

2019-02-27T01:12:33+00:00

Add driver code for the SiFive FU540 PRCI IP block.  This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.

Based on code written by Wesley Terpstra 
found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
https://github.com/riscv/riscv-linux

Boot and PLL rate change were tested on a SiFive HiFive Unleashed
board.

Signed-off-by: Paul Walmsley 
Signed-off-by: Atish Patra 
Signed-off-by: Anup Patel 
Reviewed-by: Alexander Graf