u-boot.git/drivers/clk/spacemit, branch main

clk: spacemit: k1: prune SPL clock tree

2026-07-21T08:57:13Z

K1 SPL runs from on-chip SRAM with a small pre-relocation malloc heap. Registering the full K1 clock tree would not fit, so split the tree on CONFIG_SPL_BUILD: the SPL build registers only the subset SPL needs (currently UART, SDHCI, I2C (TWSI), and their PLL/MPMU/APMU/APBC ancestors); the non-SPL build keeps the full tree. Where surviving SPL CCU definitions reference parent clocks outside that subset, use "clock-dummy", so framework parent lookups still resolve. Signed-off-by: Guodong Xu Tested-by: Songsong Zhang

clk: spacemit: k1: spawn reset device from per-syscon clock drivers

2026-07-21T08:31:10Z

The K1 reset driver in drivers/reset/spacemit/ binds by name (no DT of_match), so the per-syscon clock drivers must spawn it. Add a .bind hook to k1_mpmu_clk, k1_apbc_clk and k1_apmu_clk that calls spacemit_k1_reset_bind() to instantiate a UCLASS_RESET sibling on the same ofnode. Also introduce k1_apbc2_clk here. Its kernel DT node has #reset-cells but no #clock-cells, so the driver exists only as the binding hook for the apbc2 reset spawn. With this in place, references such as resets = <&syscon_apbc RESET_TWSI0>; in the kernel-mainline DT resolve correctly. Signed-off-by: Guodong Xu

clk: spacemit: Add support for K1 SoC

2026-07-21T08:31:10Z

The K1 SoC exposes four clock providers in the kernel mainline DT: one PLL controller ("spacemit,k1-pll") and three syscon clock nodes ("spacemit,k1-syscon-{mpmu,apbc,apmu}"). Register a separate U_BOOT_DRIVER for each. The controllers register clocks into a single CCF namespace, and a clock in one controller may parent off a clock owned by another, so a controller must register only after the controllers that own its parents have probed. Each probe forces its parent controllers up by driver: MPMU <- PLL APMU <- PLL, MPMU APBC <- PLL, MPMU, APMU Signed-off-by: Junhui Liu Signed-off-by: Raymond Mao Signed-off-by: Guodong Xu