u-boot.git/drivers/clk/starfive, branch v2024.04

clk: starfive: jh7110: Add watchdog clocks

2023-12-05T08:40:16Z

Add JH7110_SYSCLK_WDT_APB and JH7110_SYSCLK_WDT_CORE clocks for JH7110 watchdog device. Signed-off-by: Chanho Park Reviewed-by: Leo Yu-Chi Liang

clk: starfive: jh7110: Add security clocks

2023-11-02T09:45:53Z

Add STGCLK_SEC_HCLK and STGCLK_SEC_MISCAHB clocks for JH7110 TRNG device. Signed-off-by: Chanho Park Reviewed-by: Leo Yu-Chi Liang

clk: starfive: jh7110: Add of_xlate ops and macros for clock id conversion

2023-07-24T05:21:16Z

Modify the drivers to add of_xlate ops and transform clock id. Signed-off-by: Xingyu Wu Signed-off-by: Hal Feng Reviewed-by: Torsten Duwe Reviewed-by: Leo Yu-Chi Liang

clk: starfive: jh7110: Separate the PLL driver

2023-07-24T05:20:44Z

Drop the PLL part in SYSCRG driver and separate to be a single PLL driver of which the compatible is "starfive,jh7110-pll". Signed-off-by: Xingyu Wu Signed-off-by: Hal Feng Reviewed-by: Torsten Duwe Reviewed-by: Leo Yu-Chi Liang

clk: starfive: pll: Fix to use postdiv1_mask

2023-07-06T09:28:08Z

There is a problem that the rates of PLL0 and PLL1 are set incorrectly because the postdiv1_mask value is incorrectly entered when setting the pll clk reg. Modify postdiv1's mask value to be put correctly. Signed-off-by: Hoegeun Kwon Reviewed-by: Minkyu Kang

clk: starfive: Add StarFive JH7110 clock driver

2023-04-20T08:08:44Z

Add a DM clock driver for StarFive JH7110 SoC. Signed-off-by: Yanhong Wang Tested-by: Conor Dooley