u-boot.git/drivers/clk/sunxi/Makefile, branch master Unnamed repository; edit this file 'description' to name the repository. clk: sunxi: Add support for the A523 -R CCU 2025-07-27T21:57:35+00:00 Andre Przywara andre.przywara@arm.com 2024-09-13T08:01:00+00:00 d508d995d1187c3811ee4746d12f9dc106744756 Add a clock driver for the PRCM clock controller on the Allwinner A523 family of SoCs, often also used with an "r" prefix or suffix. This just describes the clock gates and reset lines for the few devices that we would need, most prominently the R_I2C device for the PMIC. Signed-off-by: Andre Przywara <andre.przywara@arm.com> 
Add a clock driver for the PRCM clock controller on the Allwinner A523
family of SoCs, often also used with an "r" prefix or suffix.
This just describes the clock gates and reset lines for the few devices
that we would need, most prominently the R_I2C device for the PMIC.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
clk: sunxi: Add support for the A523 CCU 2025-07-27T21:57:35+00:00 Andre Przywara andre.przywara@arm.com 2024-09-09T00:47:31+00:00 1d0b1d46ccfdd5fef57a4232966c905a04e21840 Add a clock driver for the main clock controller on the Allwinner A523 family of SoCs. As usual, this just describes the clock gates and reset lines for the few device that U-Boot cares about: USB, Ethernet, MMC, I2C, SPI. Signed-off-by: Andre Przywara <andre.przywara@arm.com> 
Add a clock driver for the main clock controller on the Allwinner A523
family of SoCs.
As usual, this just describes the clock gates and reset lines for the
few device that U-Boot cares about: USB, Ethernet, MMC, I2C, SPI.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
clk: sunxi: Add support for the A100/A133 CCU 2025-03-27T00:26:35+00:00 Andre Przywara andre.przywara@arm.com 2023-10-25T23:28:44+00:00 7d1936aef7c4046a89660b8f5763bde592946840 The Allwinner A100 SoC has been around for a while, and has now seemingly been replaced with its close sibling A133. Add support for the CCU, as far as used by U-Boot proper. Linux has some basic (clock and pinctrl) support for a while, so we can already use the existing binding headers. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> 
The Allwinner A100 SoC has been around for a while, and has now seemingly
been replaced with its close sibling A133.

Add support for the CCU, as far as used by U-Boot proper. Linux has some
basic (clock and pinctrl) support for a while, so we can already use the
existing binding headers.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
clk: sunxi: Add support for the D1 CCU 2023-10-22T22:41:51+00:00 Samuel Holland samuel@sholland.org 2022-05-01T03:38:37+00:00 b9a91b98e8d81d2f7fdbc0d59c544a7bbb5e3679 Since the D1 CCU binding is defined, we can add support for its gates/resets, following the pattern of the existing drivers. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> 
Since the D1 CCU binding is defined, we can add support for its
gates/resets, following the pattern of the existing drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
clk: sunxi: implement clock driver for suniv f1c100s 2022-05-22T23:37:51+00:00 George Hilliard thirtythreeforty@gmail.com 2021-07-25T23:16:23+00:00 89dd650f20ffc18372df1524ad0afbb93ce5a884 The f1c100s has a clock tree similar to those of other sunxi parts. Add support for it. Signed-off-by: George Hilliard <thirtythreeforty@gmail.com> Signed-off-by: Yifan Gu <me@yifangu.com> Acked-by: Sean Anderson <seanga2@gmail.com> [Andre: add PIO and I2C] Signed-off-by: Andre Przywara <andre.przywara@arm.com> 
The f1c100s has a clock tree similar to those of other sunxi parts.
Add support for it.

Signed-off-by: George Hilliard <thirtythreeforty@gmail.com>
Signed-off-by: Yifan Gu <me@yifangu.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
[Andre: add PIO and I2C]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
clk: sunxi: Add drivers for A31 and H6 PRCM CCUs 2021-10-11T09:46:44+00:00 Samuel Holland samuel@sholland.org 2021-09-12T14:47:25+00:00 23c83366f326fb88dd4ec40315ebae14df55ebc0 Add a driver so the clocks/resets for these peripherals (especially I2C, RSB, and UART) can be enabled using the normal uclass methods. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> 
Add a driver so the clocks/resets for these peripherals (especially I2C,
RSB, and UART) can be enabled using the normal uclass methods.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
clk: sunxi: Add a dummy clock driver for the RTC 2021-04-16T00:12:59+00:00 Samuel Holland samuel@sholland.org 2021-02-08T05:57:19+00:00 9078b67f3c968cbc3142432decc93a51780b4642 The 32kHz clock ("LOSC") on sunxi SoCs is provided by the RTC. It is used, among other things, by the XHCI controller in the H6. To be able to call clk_get_bulk() on the XHCI controller, some device needs to provide all referenced clocks. Since LOSC is a fixed-rate always-on clock, implementation is trivial. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> 
The 32kHz clock ("LOSC") on sunxi SoCs is provided by the RTC. It is
used, among other things, by the XHCI controller in the H6. To be able
to call clk_get_bulk() on the XHCI controller, some device needs to
provide all referenced clocks.

Since LOSC is a fixed-rate always-on clock, implementation is trivial.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
clk: sunxi: Add support for H616 clocks 2021-01-25T21:52:01+00:00 Jernej Skrabec jernej.skrabec@siol.net 2021-01-11T20:11:52+00:00 1dc70ffa1cd9057e9c70d15b9c8aea2779854c74 This commit introduces DM H616 clock driver. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> 
This commit introduces DM H616 clock driver.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
clk: sunxi: Add Allwinner A80 CLK driver 2019-01-18T16:49:09+00:00 Jagan Teki jagan@amarulasolutions.com 2019-01-11T10:11:46+00:00 6901aab8e35183115ae65362f3af0ea095b6c1b8 Add initial clock driver for Allwinner A80. - Implement UART bus clocks via ccu_clk_gate table for A80, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for A80, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> 
Add initial clock driver for Allwinner A80.

- Implement UART bus clocks via ccu_clk_gate table for
  A80, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for A80,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
clk: sunxi: Add Allwinner H6 CLK driver 2019-01-18T16:49:09+00:00 Jagan Teki jagan@amarulasolutions.com 2018-12-31T10:05:01+00:00 337fcdc06bad484d3af08e0fd0876e22a09358ce Add initial clock driver for Allwinner H6. - Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> 
Add initial clock driver for Allwinner H6.

- Implement UART bus clocks via ccu_clk_gate table for
  H6, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for H6,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>