u-boot.git/drivers/clk/sunxi, branch master

clk: sunxi: Staticize and constify driver ops

2026-05-18T22:56:07Z

Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut

clk: sunxi: Add MBUS Master Clock Gating Register

2026-02-03T20:45:14Z

Add MBUS Master Clock Gating Register for H6 and H616 For H6/H616, the NAND controller needs the MBUS NAND clock along with CLK_NAND0/1 and CLK_BUS_NAND. The bit locations are from H6/H616 User Manuals. Signed-off-by: Richard Genoud Signed-off-by: Michael Trimarchi

clk: sunxi: Add support for the A523 -R CCU

2025-07-27T21:57:35Z

Add a clock driver for the PRCM clock controller on the Allwinner A523 family of SoCs, often also used with an "r" prefix or suffix. This just describes the clock gates and reset lines for the few devices that we would need, most prominently the R_I2C device for the PMIC. Signed-off-by: Andre Przywara

clk: sunxi: Add support for the A523 CCU

2025-07-27T21:57:35Z

Add a clock driver for the main clock controller on the Allwinner A523 family of SoCs. As usual, this just describes the clock gates and reset lines for the few device that U-Boot cares about: USB, Ethernet, MMC, I2C, SPI. Signed-off-by: Andre Przywara

clk: sunxi: Add support for the A100/A133 CCU

2025-03-27T00:26:35Z

The Allwinner A100 SoC has been around for a while, and has now seemingly been replaced with its close sibling A133. Add support for the CCU, as far as used by U-Boot proper. Linux has some basic (clock and pinctrl) support for a while, so we can already use the existing binding headers. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec

clk: sunxi: a80: Fix reset description

2024-10-09T23:23:41Z

Clock gates and reset lines share a common structure in the sunxi clock driver descriptions, but use different flags to tell them apart. The description of the Allwinner A80 MMC clock reset lines was erroneously using the "GATE" macro, which made the reset driver ignore that entry, complaining with: sunxi_set_reset: (RST-reset:#0) unhandled Change that to the correct "RESET" macro, to make the reset driver happy. Fixes e0c7ce7e52b7 ("sunxi: clk: A80: add MMC clock support") Signed-off-by: Andre Przywara

clk: sunxi: add EMAC and EPHY clocks and resets for the V3s SoC

2024-07-15T21:18:16Z

Add the clock gate registers as well as the reset register bits for the EMAC and EPHY for the V3s. These are needed by the sun8i network driver. Signed-off-by: Michael Walle Reviewed-by: Andre Przywara

Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"

2024-05-20T19:35:03Z

As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman Signed-off-by: Tom Rini

Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""

2024-05-19T14:16:36Z

When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman Signed-off-by: Tom Rini

clk: Remove and add needed includes

2024-05-07T14:00:41Z

Remove from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini