u-boot.git/drivers/clk/ti, branch master

clk: ti: Remove AM33xx dependency

2026-06-17T15:50:35Z

The clock controller driven by this driver exists on other OMAP platforms than the AM33xx. Yet, it uses functions provided by arch/arm/mach-omap2/am33xx/clock.c making it unusable by other OMAPs. Replace am33xx-specific do_{enable/disable}_clocks() with new static functions implemented locally. Replace the am33xx-specific clock header with the one shared by all OMAP platforms. Signed-off-by: Bastien Curutchet

Merge patch series "clk: ti: Cleanup common functions and omap-cm"

2025-12-12T21:20:54Z

Markus Schneider-Pargmann (TI.com) says: This series cleans up the direct dependency of ARCH_OMAP2PLUS to compile ti/clk.c which holds common functions for other clock drivers. It creates its own config symbols for these common functions and for the omap-cm driver as well. The omap-cm driver config symbol is added as default enabled. Link: https://lore.kernel.org/r/20251128-topic-am33-clk-regmap-dep-v2026-01-v2-0-451b4f4e7e85@baylibre.com/

clk: ti: omap4-cm: Add Kconfig symbol

2025-12-12T21:18:27Z

Add a Kconfig symbol for this stub driver to avoid clock dependencies on an architecture symbol. Enable it by default. Signed-off-by: Markus Schneider-Pargmann (TI.com) Reviewed-by: Tom Rini

clk: ti: Split common omap2plus functions into new symbol

2025-12-12T21:18:27Z

Create a new symbol for the common clock functions used by some of the omap2plus clock drivers. These drivers now select this new symbol when they need the functions. Note these common functions are not ARCH_OMAP2PLUS specific. Note that the common functions are using regmap, so select it here. Reviewed-by: Tom Rini Signed-off-by: Markus Schneider-Pargmann (TI.com)

clk: ti: Tighten some TI clock driver dependencies

2025-12-05T21:04:52Z

Attempting to build with "allyesconfig" means that we try and build all available options for the sandbox platforms. Doing so exposes that the drivers under drivers/clk/ti/ can only be compiled or linked on ARCH_OMAP2PLUS platforms as some drivers require platform specific headers while other drivers depend on these first drivers to link. Express those requirements in Kconfig as well. Reviewed-by: Manorit Chawdhry Signed-off-by: Tom Rini

clk: Tighten some clock driver dependencies

2025-10-28T18:25:23Z

A few clock drivers cannot build without access to some platform specific header files. Express those requirements in Kconfig as well. Signed-off-by: Tom Rini

clk: ti: fix K3 clock driver help texts

2025-10-04T18:51:01Z

Add "in SPL" to the SPL related driver help texts. Signed-off-by: Yegor Yefremov Reviewed-by: Quentin Schulz

arm: mach-k3: j721e: Split out J7200 SoC support from J721e

2025-04-06T00:28:02Z

Currently in j721e_init.c we check which firewalls to remove using the board configuration (e.g CONFIG_TARGET_J721E_R5_EVM). We do this as J721e and J7200 have different IP and firewalls but use the same SoC definition (SOC_K3_J721E) even though they are different SoCs. The idea was they would be similar enough that they both could use the same SoC config to help with common code sharing. Board checks would then be used differentiate. This has grown far too messy to maintain any more, especially now that there is more than one board using J721e (EVM, SK, Beagle AI64). As differentiation is done based on board, every one of these boards would have to have checks added for them. Instead let's split J7200 support out from J721e like how normal new SoC support is done. This patch touches several subsystems and could not be split much better as when we add SOC_K3_J7200 we want to make use of it in all spots that once used the combined SOC_K3_J721E so we can turn off SOC_K3_J721E when building for J7200 boards. Signed-off-by: Andrew Davis

arm: mach-k3: j742s2: Introduce clock and device files for J742S2 SoC

2025-04-03T17:37:46Z

Re-use j784s4 clocks and power domains for j742s2 family of device. Reviewed-by: Udit Kumar Signed-off-by: Manorit Chawdhry

clk: ti: clk-k3-pll: Add additional robustness steps to the PLL sequence

2024-12-06T22:38:16Z

Based on the recommendation from HW team make modifications to the sequence for more robustness. - Unlock the PLL registers - Enable external bypass - Disable the PLL - Program pllm and pllf - Program Ref divider - Enable other PLL controls like DSM_EN, DAC_EN,etc - Enable calibration if available - Enable PLL - Wait for PLL lock and Calibration lock - Remove external bypass Re-write the full sequence from scratch as the previous sequence was way off and keep it in a single commit for bisectability. Signed-off-by: Manorit Chawdhry