u-boot.git/drivers/clk, branch master

treewide: Kconfig: use bool instead of tristate

2026-07-10T21:45:57Z

U-Boot does not support modules, so having tristate options is useless. Therefore this patch does a blind replace of all tristate options to bool tree-wide. Signed-off-by: Anshul Dalal Reviewed-by: Heiko Schocher Reviewed-by: Quentin Schulz Reviewed-by: Siddharth Vadapalli Reviewed-by: Neha Malcom Francis Reviewed-by: Romain Gantois Reviewed-by: Simon Glass

Merge patch series "pinctrl: add support of Airoha SoCs"

2026-07-08T19:42:17Z

Mikhail Kshevetskiy says: This patch series add pin controller and gpio driver support for EN7523/ AN7581/AN7583 SoCs. The driver based on official linux airoha pinctrl and gpio driver with Matheus Sampaio Queiroga changes. The original Matheus Sampaio Queiroga driver can be taken from the repo: https://sirherobrine23.com.br/airoha_en7523/kernel/src/branch/airoha_en7523_pinctrl Additionally in the EN7523 case the patches removes existing gpio dts nodes and replaces them with pinctrl node. It should not be very dangerous, because: * No official EN7523 gpio support present in U-Boot * Legacy Linux EN7523 GPIO driver is mostly abandoned * The same driver is planned for upstream linux/openwrt This patchset includes bitfield.h patches created for Linux kernel by Geert Uytterhoeven. It suits U-Boot fine. I preserve original author and original commit messages. Please note me, if there is a better way. The patches were tested on EN7523/AN7581/AN7583 boards. Link: https://lore.kernel.org/r/20260703115627.2317120-1-mikhail.kshevetskiy@iopsys.eu

clk: renesas: rcar-cpg-lib: Convert to common field_{get, prep}() helpers

2026-07-08T19:29:18Z

Drop the driver-specific field_get() and field_prep() macros, in favor of the globally available variants from . Signed-off-by: Mikhail Kshevetskiy

clk: renesas: #undef field_{get, prep}() before definition

2026-07-08T19:29:18Z

Prepare for the advent of globally available common field_get() and field_prep() macros by undefining the symbols before defining local variants. This prevents redefinition warnings from the C preprocessor when introducing the common macros later. Signed-off-by: Mikhail Kshevetskiy

Merge branch 'next'

2026-07-07T00:26:12Z

clk/qcom: milos: Add TCSRCC clocks

2026-06-30T11:04:59Z

With a recent change to the UFS driver, now all clocks need to be available. Add all the clocks from the TCSRCC block on Milos. Signed-off-by: Luca Weiss Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260625-milos-ufs-fix-v1-2-b0923dabc35f@fairphone.com Signed-off-by: Casey Connolly

clk/qcom: milos: Add remaining UFS clocks

2026-06-30T11:04:59Z

With a recent change to the UFS driver, now all clocks need to be available. Add them. Signed-off-by: Luca Weiss Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260625-milos-ufs-fix-v1-1-b0923dabc35f@fairphone.com Signed-off-by: Casey Connolly

Merge patch series "arm: aspeed: add initial AST2700 SoC support"

2026-06-29T21:29:56Z

Ryan Chen says: AST2700 is the 8th generation of Integrated Remote Management Processor introduced by ASPEED Technology Inc. It is a Board Management Controller (BMC) SoC family with a dual-die architecture: SoC0 ("CPU" die with four ARM Cortex-A35 application cores) and SoC1 ("IO" die with peripherals) each SoC have its own SCU PLLs, clock dividers and reset domains. Link: https://lore.kernel.org/r/20260612-ast2700_clk-v4-0-9bea29cfdc39@aspeedtech.com

clk: ast2700: add clock driver support

2026-06-29T19:43:20Z

Add clock controller driver for the dual-die AST2700 SoC. The chip has two SCUs (SoC0/CPU at 0x12c02000, SoC1/IO at 0x14c02000), each with its own PLLs (HPLL/APLL/DPLL/MPLL), clock dividers and clock gate controls. This commit registers two UCLASS_CLK drivers matching "aspeed,ast2700-scu0" and "aspeed,ast2700-scu1". Signed-off-by: Ryan Chen

clk: imx: imx8mq: Fix iMX8MQ PLL issue

2026-06-27T17:53:01Z

The fractional PLL used on iMX8MQ is not pll14xx, it is different PLL and not exist in u-boot. Add this fractional PLL driver and update iMX8MQ clock driver to adapt this fraction PLL. Fixes: 11c8ab01f3ed ("clk: imx8mq: Add a clock driver for the imx8mq") Signed-off-by: Ye Li Reviewed-by: Peng Fan