u-boot.git/drivers/clk, branch next

Merge patch series "arm: aspeed: add initial AST2700 SoC support"

2026-06-29T21:29:56Z

Ryan Chen says: AST2700 is the 8th generation of Integrated Remote Management Processor introduced by ASPEED Technology Inc. It is a Board Management Controller (BMC) SoC family with a dual-die architecture: SoC0 ("CPU" die with four ARM Cortex-A35 application cores) and SoC1 ("IO" die with peripherals) each SoC have its own SCU PLLs, clock dividers and reset domains. Link: https://lore.kernel.org/r/20260612-ast2700_clk-v4-0-9bea29cfdc39@aspeedtech.com

clk: ast2700: add clock driver support

2026-06-29T19:43:20Z

Add clock controller driver for the dual-die AST2700 SoC. The chip has two SCUs (SoC0/CPU at 0x12c02000, SoC1/IO at 0x14c02000), each with its own PLLs (HPLL/APLL/DPLL/MPLL), clock dividers and clock gate controls. This commit registers two UCLASS_CLK drivers matching "aspeed,ast2700-scu0" and "aspeed,ast2700-scu1". Signed-off-by: Ryan Chen

clk: imx6q: use clk_divider_table instead of fixed factor for pll5 divs

2026-06-27T02:02:46Z

Now that non-linear clk divider tables are supported, replace the fixed factor implementation with the proper divider, which allows more fine control over clock rates. Signed-off-by: Brian Ruley

clk: clk-divider: add clk_register_divider_table()

2026-06-27T02:02:46Z

The existing clk_register_divider() only supports linear or power-of-two divider mappings. Some hardware (e.g. i.MX6 PLL5 post_div and video_div) uses non-linear register-value-to-divisor mappings that require a lookup table. Add clk_register_divider_table() which accepts a clk_div_table, and reimplement clk_register_divider() as a wrapper passing table=NULL. Signed-off-by: Brian Ruley

clk: imx6q: configure ldb clock selectors

2026-06-27T02:02:46Z

A hardware bug prevents LDB clock selectors from being configured later on non-plus i.MX6QD variants, so let's set the desired configuration in the probe before we register them. We also have to make the necessary clock functions available in XPL builds. Signed-off-by: Brian Ruley

clk: imx6q: add missing pll bypasses

2026-06-27T02:02:46Z

After reset, all PLLs are bypassed by default so unbypass them so that dependent clocks can function correctly. Signed-off-by: Brian Ruley

clk: imx6q: guard video clocks behind config

2026-06-27T02:02:46Z

Do not touch the video clocks unless explicitly required by the configuration. This avoids the issue of the binary size increase on SPL builds that do not enable video. For those that do, they should increase the size limit to fit the new code and data. Signed-off-by: Brian Ruley

clk: imx6q: cosmetic: keep pll definitions together

2026-06-27T02:02:46Z

Make it easier to reason about by keeping similar clocks grouped together. While at it, fix comment spacing. Signed-off-by: Brian Ruley

Kconfig: drivers: restyle remaining

2026-06-25T21:00:58Z

Restyle all Kconfigs for the rest of "drivers": Menu entries : no space left Menu attributes: 1 TAB Help text : 1 TAB + 2 spaces Replace '---help---' by 'help' Signed-off-by: Johan Jonker [trini: Add missing indentation on a few more multi-paragraph help texts] Signed-off-by: Tom Rini

Merge tag 'v2026.07-rc5' into next

2026-06-22T22:42:41Z

Prepare v2026.07-rc5