u-boot.git/drivers/clk, branch next

Merge tag 'v2026.07-rc3' into next

2026-05-25T17:35:35+00:00

Prepare v2026.07-rc3

clk: renesas: Add Renesas R-Car R8A78000 X5H CPG clock driver

2026-05-21T19:48:05+00:00

Add Renesas R-Car R8A78000 X5H CPG clock driver, which serves as a
remap driver between DT clock IDs and SCMI clock IDs in case U-Boot
runs on the Cortex-A, and as a trivial clock driver for RSIP.

The R-Car X5H SCP firmware uses different SCMI clock IDs in different
versions of the SCP firmware, which makes this remapping necessary.
The SCMI base protocol version is updated for each new SCP firmware
version, it is therefore possible to determine which SCP firmware
version is running on the platform from the base protocol and then
determine which remapping table to use for DT clock ID to SCMI clock
ID remapping.

Currently supported versions are SCP 4.28, 4.31, 4.32 .

The DT clock ID to SCMI clock ID remap and call mechanism is a bit
complex. The driver looks up the SCMI clock protocol device on probe
and stores pointer to it in private data. On each clock request which
has to be remapped, the device sequence ID of this SCMI clock protocol
device is incremented by the remapped SCMI clock ID + 1 and used to
look up matching clock device by sequence number. If the device is
found, it is converted to clock, which can be used in regular clock
operations. This look up has to be done because the SCMI clock driver
registers a subdevice for each clock, and this look up is the only way
to find the correct SCMI clock subdevice. Since the SCMI device and
the clock subdevices are registered in the same function, we can depend
on the device sequence numbers to be monotonically incrementing, with
SCMI clock protocol device being sequence number N, the first SCMI
clock subdevice being sequence number N+1 and so on.

In case of RSIP, all clocks are already enabled by BootROM or early
SoC initialization code, the driver therefore only acts as a stub.

Signed-off-by: Marek Vasut

clk: sunxi: Staticize and constify driver ops

2026-05-18T22:56:07+00:00

Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut

clk: ast2600: Staticize and constify driver ops

2026-05-18T22:56:07+00:00

Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut

clk: ast2500: Staticize and constify driver ops

2026-05-18T22:56:07+00:00

Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut

clk/qcom: qcm2290: Fix vote_bit of gpll6 clock

2026-05-18T09:06:02+00:00

This changes the vote_bit same as enable_mask in Linux clock driver.

Fixes: 3ddc67573fab ("clk/qcom: qcm2290: Add SDCC1 apps clock frequency table")
Signed-off-by: Biswapriyo Nath 
Link: https://patch.msgid.link/20260515-ufs-sm61x5-v2-2-0a35d083d2da@gmail.com
Signed-off-by: Casey Connolly

clk/qcom: Add SM6125 clock driver

2026-05-18T09:04:14+00:00

Add clock driver for the GCC block found in the SM6125 SoC.

Signed-off-by: Biswapriyo Nath 
Reviewed-by: Casey Connolly 
soc98: input: 1 [x] mmc@4784000.cd-gpios
soc98: input: 0 [x] mmc@4784000.cd-gpios
Link: https://patch.msgid.link/20260204-sm6125-clk-pinctrl-v1-1-9cf4c556557a@gmail.com
Signed-off-by: Casey Connolly

clk: qcom: sc7280: Add UFS clock support

2026-05-18T09:04:13+00:00

Add UFS clock support for sc7280 including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg 
Signed-off-by: Balaji Selvanathan 
Reviewed-by: Casey Connolly 
Link: https://patch.msgid.link/20260427-ufs_clk-v2-5-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly

clk: qcom: qcs615: Add UFS clock support

2026-05-18T09:04:13+00:00

Add UFS clock support for qcs615 including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg 
Signed-off-by: Balaji Selvanathan 
Reviewed-by: Casey Connolly 
Link: https://patch.msgid.link/20260427-ufs_clk-v2-4-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly

clk: qcom: sa8775p: Add UFS clock support

2026-05-18T09:04:13+00:00

Add UFS clock support for SA8775P including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg 
Signed-off-by: Balaji Selvanathan 
Reviewed-by: Casey Connolly 
Link: https://patch.msgid.link/20260427-ufs_clk-v2-3-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly