u-boot.git/drivers/clk, branch next

Merge tag 'i2c-updates-for-2026.10-next' of https://git.u-boot-project.org/u-boot/custodians/hs/u-boot-i2c into next

2026-08-25T17:37:49Z

i2c updates for 2026.10-next - i2c/clk: spacemit: k1: fix I2C bus configuration and clock handling from Junhui Reviewed by Yao Zi and myself.

Merge tag 'mediatek-for-next-2026-08-24' of https://git.u-boot-project.org/u-boot/custodians/u-boot-mediatek into next

2026-08-25T17:36:46Z

* New HDMI PHY and I2C DDC drivers, default EDID_ADDR macro * MT8189 clock qualifier fix * Phase-aware PSCI reset (MT8195/MT8365) * dwc_eth_qos MT8366 support * MediaTek TPHY v3 hardware support * mtk_snor mt8188/mt8189 compatible-string cleanup * MT6358/MT6366 PMIC regulator + pwrap support * MediaTek pinctrl Kconfig cleanup (per-SoC symbols → single driver + TARGET_*) * New MT8366 pinctrl driver + dt-bindings header * MediaTek serial driver clock-handling fixes

clk: spacemit: k1: remove bus gate from TWSI functional clocks

2026-08-25T06:22:24Z

The TWSI functional clocks incorrectly include both the functional clock enable bit and the bus clock enable bit in their gate masks. The device tree and the full clock tree model the bus clocks separately. Remove the bus clock enable bit from the functional clock gate masks so that the functional and bus clocks are controlled independently. Keep the combined gate for TWSI8 because its clock control register is write-only and therefore cannot be safely shared by two clock instances. Fixes: 3aa2882a3e1a ("clk: spacemit: Add support for K1 SoC") Reviewed-by: Yao Zi Signed-off-by: Junhui Liu

clk: spacemit: k1: add TWSI bus clocks to SPL

2026-08-25T06:22:24Z

The K1 device tree describes separate functional and bus clocks for TWSI controllers, but the SPL clock tree currently only provides their functional clocks. Add the bus clocks for TWSI2 and TWSI8, which are the TWSI controllers currently used in SPL, along with their required parent clock chain. TWSI8 uses a fixed-factor bus clock because its write-only clock control register requires the functional and bus gate bits to remain combined in a single clock instance. Reviewed-by: Yao Zi Signed-off-by: Junhui Liu

drivers: clk: n5x: Add support for enable/disable API

2026-08-19T16:36:04Z

Update N5X clock driver to support enabling or disabling the peripheral clocks via clock driver model APIs. The caller will pass the clock ID to this driver and the driver will then proceed to manipulate the desired bit in the N5X clock manager peripheral PLL register based on the given clock ID. N5X_L4_SYS_FREE_CLK is a free-running clock with no gate control in hardware, therefore attempting to enable or disable it is not applicable. Return -EOPNOTSUPP for this clock ID and treat it as a no-op in socfpga_clk_enable() and socfpga_clk_disable(). Signed-off-by: Alif Zakuan Yuslaimi Signed-off-by: Chen Huei Lok

drivers: clk: altera: arria10: Fix wrong API used for memory free

2026-08-19T16:36:03Z

Fix the wrong API used for memory free. Signed-off-by: Dinesh Maniyam

clk: altera: agilex: Update sync to async mode config in clk pll

2026-08-19T16:36:03Z

Remove MEMBUS_CLKSLICE_REG source synchronous mode configuration to run as source asynchronous mode. Switching the HPS PLL to async mode improves resistance to clock marginality issues such as F2S clk to HPS PLL Signed-off-by: Alif Zakuan Yuslaimi Signed-off-by: Boon Khai Ng

clk: s10: Refactor S10 clock driver

2026-08-19T15:07:05Z

Refactor Stratix10 clock manager driver to support driver model, following Agilex clock driver. Create a new clock driver, clk-s10.c, for Stratix10 which supports the driver model. This allows several APIs such as enable/disable clock, and get clock rate to be supported. This driver will be initialized during SPL to bring up the clock as early as possible. The clock initialization process are refactored into this new driver from clock_manager_s10.c during clock driver probe. Excluding Stratix10 from legacy method of obtaining clkmgr base address in mach-socfpga/misc.c as the base address is already obtained during clock driver probe during SPL initialization. Signed-off-by: Alif Zakuan Yuslaimi

clk: mediatek: mt8189: add missing qualifiers

2026-08-13T16:35:20Z

Add a missing const and a missing static qualifier to a couple of lookup tables. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260731-mtk-clk-mt8189-fix-missing-qualifiers-v1-1-92f3f0e44817@baylibre.com Signed-off-by: David Lechner

clk: rockchip: pll: fix overflow and drop manual two's complement on RK3588/RK3576

2026-08-12T14:55:03Z

The TRM defines the fractional PLL adjustment coefficient as a signed two's complement number, 16 bits wide, so store and use it as such to avoid confusion and enable proper signed arithmetics, promoting operands with automatic sign extension. This also fixes an overflow when the current rk3588_pll_get_rate calculates the fractional component in 32 bits before assigning it to a 64-bit holding variable, given that OSC_HZ is 24000000U and k can be from -32768 to 32767. Fixes: b851c006a150 ("clk: rockchip: pll: Add pll_rk3588 type for rk3588") Reviewed-by: Quentin Schulz Signed-off-by: Alexey Charkov Link: https://patch.msgid.link/20260723-rk3588-fracpll-v2-5-382d113f3a80@flipper.net Signed-off-by: Quentin Schulz