u-boot.git/drivers/clk, branch v2016.05 Unnamed repository; edit this file 'description' to name the repository. clk: uniphier: add Media I/O clock driver support for PH1-LD20 2016-04-24T00:54:10+00:00 Masahiro Yamada yamada.masahiro@socionext.com 2016-04-21T05:43:21+00:00 306d37e949ed63b6d937589793f0ed0659f58adf PH1-LD20 needs this for its SD card controller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 
PH1-LD20 needs this for its SD card controller.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
clk: uniphier: use devm_get_addr() to get base address 2016-03-31T15:17:08+00:00 Masahiro Yamada yamada.masahiro@socionext.com 2016-03-24T13:32:39+00:00 45a3b1fd6ca524bebf5b9ce771ad1fb12f3514ce Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 
Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties.  (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
clk: uniphier: add Media I/O clock driver for UniPhier SoCs 2016-02-14T07:36:13+00:00 Masahiro Yamada yamada.masahiro@socionext.com 2016-02-02T12:11:32+00:00 48264d9beba2ccc18b9497944048eea135883529 This is the initial commit for the UniPhier clock drivers. Currently, only the Media I/O clock is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 
This is the initial commit for the UniPhier clock drivers.
Currently, only the Media I/O clock is supported.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
drivers: clk: Add clock driver for Microchip PIC32 Microcontroller. 2016-02-01T21:14:00+00:00 Purna Chandra Mandal purna.mandal@microchip.com 2016-01-28T10:00:11+00:00 a0e7908326b9dcde4c27dbbcbc52ccbf9e009255 PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers and dividers capable of supplying clock to various controllers on or off-chip. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> 
PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers
and dividers capable of supplying clock to various controllers
on or off-chip.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
rockchip: spl: Support full-speed CPU in SPL 2016-01-22T03:42:37+00:00 Simon Glass sjg@chromium.org 2016-01-22T02:45:17+00:00 dae594f2105b08ce76aa6b3b02433abb0796be51 Add a feature which speeds up the CPU to full speed in SPL to minimise boot time. This is only supported for certain boards (at present only jerry). Signed-off-by: Simon Glass <sjg@chromium.org> 
Add a feature which speeds up the CPU to full speed in SPL to minimise
boot time. This is only supported for certain boards (at present only
jerry).

Signed-off-by: Simon Glass <sjg@chromium.org>
rockchip: rk3288: clock: Fix various minor errors 2016-01-22T03:42:37+00:00 Simon Glass sjg@chromium.org 2016-01-22T02:45:15+00:00 c87c129f7f754324a702a302edbbdeb752215e4c Fix a number of small errors which were found in reviewing the clock code. Signed-off-by: Simon Glass <sjg@chromium.org> 
Fix a number of small errors which were found in reviewing the clock code.

Signed-off-by: Simon Glass <sjg@chromium.org>
rockchip: clk: Add support for clocks needed by the displays 2016-01-22T03:42:36+00:00 Simon Glass sjg@chromium.org 2016-01-22T02:45:02+00:00 830a6081706e3f07bdd2a0fd7de131516d2a92a9 The displays need to use NPLL and also select some new peripheral clocks. Add support for these to the clock driver. Signed-off-by: Simon Glass <sjg@chromium.org> 
The displays need to use NPLL and also select some new peripheral clocks.
Add support for these to the clock driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
rockchip: Rename the CRU_MODE_CON fields 2016-01-22T03:42:36+00:00 Simon Glass sjg@chromium.org 2016-01-22T02:45:01+00:00 009741fbaead2daf003ac8487ac671d32477206e These should match the datasheet naming. Adjust them. Signed-off-by: Simon Glass <sjg@chromium.org> 
These should match the datasheet naming. Adjust them.

Signed-off-by: Simon Glass <sjg@chromium.org>
rockchip: clk: Make rkclk_get_clk() SoC-specific 2016-01-22T03:42:35+00:00 Simon Glass sjg@chromium.org 2016-01-22T02:44:05+00:00 5ddf5d7705d2c2b59282ebd37aa2018460274e89 The current method assumes that clocks are numbered from 0 and we can determine a clock by its number. It is safer to use an ID in the clock's platform data to avoid the situation where another clock is bound before the one we expect. Move the existing code into rk3036 since it still works there. Add a new implementation for rk3288. Signed-off-by: Simon Glass <sjg@chromium.org> 
The current method assumes that clocks are numbered from 0 and we can
determine a clock by its number. It is safer to use an ID in the clock's
platform data to avoid the situation where another clock is bound before
the one we expect.

Move the existing code into rk3036 since it still works there. Add a new
implementation for rk3288.

Signed-off-by: Simon Glass <sjg@chromium.org>
dm: clk: Add a simple version of clk_get_by_index() 2016-01-22T03:42:35+00:00 Simon Glass sjg@chromium.org 2016-01-22T02:44:00+00:00 a4b10c088c4f6ef2e2bba33e8cfea369bcbbce44 This function adds quite a bit of code to SPL and we probably don't need all the features in SPL. Add a simple version (for SPL only) to save space. Signed-off-by: Simon Glass <sjg@chromium.org> 
This function adds quite a bit of code to SPL and we probably don't need
all the features in SPL. Add a simple version (for SPL only) to save space.

Signed-off-by: Simon Glass <sjg@chromium.org>