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<title>u-boot.git/drivers/clk, branch v2016.11-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/clk?h=v2016.11-rc2</id>
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<updated>2016-10-13T19:54:10Z</updated>
<entry>
<title>libfdt: Bring in upstream stringlist functions</title>
<updated>2016-10-13T19:54:10Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-10-02T23:59:28Z</published>
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<id>urn:sha1:b02e4044ff8ee1f6ac83917a39514172a9b449fb</id>
<content type='text'>
These have now landed upstream. The naming is different and in one case the
function signature has changed. Update the code to match.

This applies the following upstream commits by
Thierry Reding &lt;treding@nvidia.com&gt; :

   604e61e fdt: Add functions to retrieve strings
   8702bd1 fdt: Add a function to get the index of a string
   2218387 fdt: Add a function to count strings

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>clock: implement a driver for the Tegra CAR</title>
<updated>2016-09-27T16:11:02Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2016-09-13T16:45:59Z</published>
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<id>urn:sha1:4a332d3ee770bd6b633fd3abba741451b17156bc</id>
<content type='text'>
Implement a clock uclass driver for the Tegra CAR. This allows clients to
use standard clock APIs on Tegra. This device is intended to be
instantiated by the core Tegra CAR driver, rather than being instantiated
directly from DT. The implementation uses the existing custom Tegra-
specific clock APIs to avoid coupling the series with significant
refactoring of the existing Tegra clock/clock code. The driver currently
only supports peripheral clocks, and avoids support for other clocks such
as PLLs and external clocks. This should be sufficient to convert over all
Tegra peripheral drivers, and avoids a complex implementation which calls
different Tegra-specific clock APIs based on the type of clock being
manipulated.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-rockchip</title>
<updated>2016-09-22T20:51:19Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-09-22T20:51:19Z</published>
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<id>urn:sha1:201c9d884dcadb4e76981c30e9915f73de2d09b5</id>
<content type='text'>
</content>
</entry>
<entry>
<title>clk: uniphier: allow to have clock node under syscon node</title>
<updated>2016-09-22T16:00:39Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2016-09-21T22:42:22Z</published>
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<id>urn:sha1:6dc5b6b1ff030a811d1747c19009d9f3b0908099</id>
<content type='text'>
To sync the DT binding with Linux, the register base must be taken
from the parent syscon node.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>clk: uniphier: move U_BOOT_DRIVER entry to core code</title>
<updated>2016-09-22T16:00:39Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2016-09-21T22:42:21Z</published>
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<id>urn:sha1:102e318777a5ee400e75996e99570d4f5bbde4aa</id>
<content type='text'>
Move U_BOOT_DRIVER() entry from the data file (clk-uniphier-mio.c)
to the core support file (clk-uniphier-core.c) because I do not want
to repeat the driver boilerplate when I add more clock data.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>clk: uniphier: constify clock data arrays/structures</title>
<updated>2016-09-22T16:00:39Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2016-09-21T22:42:20Z</published>
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<id>urn:sha1:3524d47c7906be1e3d8502b7af39e4c038584286</id>
<content type='text'>
Clarify these clock data are constant.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>clk: rk3288: add PWM clock get rate</title>
<updated>2016-09-22T13:57:02Z</updated>
<author>
<name>Kever Yang</name>
<email>kever.yang@rock-chips.com</email>
</author>
<published>2016-08-12T09:57:05Z</published>
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<id>urn:sha1:4f0b8efa50a543efd407fb8b2e9ad0de49467a15</id>
<content type='text'>
This patch add clk_get_rate for PWM device.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>clk: rk3399: add pmucru controller support</title>
<updated>2016-09-22T13:57:02Z</updated>
<author>
<name>Kever Yang</name>
<email>kever.yang@rock-chips.com</email>
</author>
<published>2016-08-12T09:47:15Z</published>
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<id>urn:sha1:5e79f443550a0aac1a4a118d956a48177972aa51</id>
<content type='text'>
pmucru is a module like cru which is a clock controller manage some PLL
and module clocks.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>clk: boston: Providea simple driver for Boston board clocks</title>
<updated>2016-09-21T13:04:32Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-09-08T06:47:38Z</published>
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<id>urn:sha1:dd7c749474e0976cfc7e78dc9032d7fa8b9b9632</id>
<content type='text'>
Add a simple driver for the clocks provided by the MIPS Boston
development board. The system provides information about 2 clocks whose
rates are fixed by the bitfile flashed in the boards FPGA, and this
driver simply reads the rates of these 2 clocks.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-atmel</title>
<updated>2016-08-15T21:31:23Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-08-15T21:31:23Z</published>
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<id>urn:sha1:0fcb9f07a1d086fc6951c08d2fc1cf6048bd54e2</id>
<content type='text'>
</content>
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