u-boot.git/drivers/clk, branch v2017.03

Merge git://git.denx.de/u-boot-dm

2017-02-08T21:24:44+00:00

aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation

2017-02-08T20:56:30+00:00

Fix H-PLL and M-PLL rate calculation in ast2500 clock driver.
Without this fix, valid setting can lead to division by zero
when requesting the rate of H-PLL or M-PLL clocks.

Signed-off-by: Maxim Sloyko 
Reviewed-by: Simon Glass

dm: core: Replace of_offset with accessor

2017-02-08T13:12:14+00:00

At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass

clk: uniphier: fix compatible strings for Pro5, PXs2, LD20 SD clock

2017-01-29T11:59:08+00:00

I missed to update them when DT files were resynced with Linux.

Signed-off-by: Masahiro Yamada

aspeed: Add basic ast2500-specific drivers and configuration

2017-01-28T19:04:29+00:00

Clock Driver

This driver is ast2500-specific and is not compatible with earlier
versions of this chip. The differences are not that big, but they are
in somewhat random places, so making it compatible with ast2400 is not
worth the effort at the moment.

SDRAM MC driver

The driver is very ast2500-specific and is completely incompatible
with previous versions of the chip.

The memory controller is very poorly documented by Aspeed in the
datasheet, with any mention of the whole range of registers missing. The
initialization procedure has been basically taken from Aspeed SDK, where
it is implemented in assembly. Here it is rewritten in C, with very limited
understanding of what exactly it is doing.
Reviewed-by: Simon Glass

clk: zynqmp: Add clock driver support for zynqmp

2017-01-10T09:18:12+00:00

Add basic clock driver support for zynqmp which
sets the required clock for GEM controller

Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Michal Simek 
Reviewed-by: Simon Glass

rockchip: clk: Support setting ACLK

2016-11-26T00:59:31+00:00

Add basic support for setting the ARM clock, since this allows us to run
at maximum speed in U-Boot. Currently only a single speed is supported
(1.8GHz).

Signed-off-by: Simon Glass

rockchip: rk3288: Move rockchip_get_cru() out of the driver

2016-10-30T19:29:06+00:00

This function is called from outside the driver. It should be placed into
common SoC code. Move it.

Signed-off-by: Simon Glass 
Reviewed-by: Kever Yang

rockchip: rk3399: Move rockchip_get_cru() out of the driver

2016-10-30T19:29:06+00:00

This function is called from outside the driver. It should be placed into
common SoC code. Move it.

Also rename the driver symbol to be more consistent with the other rockchip
clock drivers.

Signed-off-by: Simon Glass 
Reviewed-by: Kever Yang

rockchip: rk3036: Move rockchip_get_cru() out of the driver

2016-10-30T19:29:06+00:00

This function is called from outside the driver. It should be placed into
common SoC code. Move it.

Also rename the driver symbol to be more consistent with the other rockchip
clock drivers.

Signed-off-by: Simon Glass 
Reviewed-by: Kever Yang