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<title>u-boot.git/drivers/clk, branch v2017.05</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>rockchip: clk: rk3399: 24MHz is not a power of 2</title>
<updated>2017-04-05T02:01:57+00:00</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-03-24T18:35:37+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ba3bf3879ecb10e3da0892fe42d13ae19ca2439f'/>
<id>ba3bf3879ecb10e3da0892fe42d13ae19ca2439f</id>
<content type='text'>
The clock driver for the RK3399 mistakenly used (24 * 2^20) where it
should have used (24 * 10^6) in a few calculations.

This commits fixes this.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
The clock driver for the RK3399 mistakenly used (24 * 2^20) where it
should have used (24 * 10^6) in a few calculations.

This commits fixes this.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: clk: rk3399: add clocking support for Ethernet</title>
<updated>2017-04-05T02:01:57+00:00</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-03-24T18:24:25+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=65d833038e27656f881f8902289152879a5c3d99'/>
<id>65d833038e27656f881f8902289152879a5c3d99</id>
<content type='text'>
The Ethernet driver for the RK3288/3399 GMAC makes sure that the clock
is ungated through a call to clk_set_rate(...). Even though nothing
needs to be done on the RK3399 (the clock gates are open and the clock
is external), we need to implement enough support to at least return
success to enable driver probing.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The Ethernet driver for the RK3288/3399 GMAC makes sure that the clock
is ungated through a call to clk_set_rate(...). Even though nothing
needs to be done on the RK3399 (the clock gates are open and the clock
is external), we need to implement enough support to at least return
success to enable driver probing.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: clk: rk3399: fix warnings for unused variables in SPL/non-SPL</title>
<updated>2017-04-05T02:01:57+00:00</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-03-24T18:24:24+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=61dff33b52335e674cf175b75e87d3300ded46d8'/>
<id>61dff33b52335e674cf175b75e87d3300ded46d8</id>
<content type='text'>
Due to differences in the code paths for SPL and non-SPL, some static
constant structures remain unused in each build variant. This raises
warnings with recent GCC versions (we currently use GCC-6.3).

The warnings addressed in this commit (by matching #if conditions for
the variable definition with their uses) are:

* for the SPL build:
    drivers/clk/rockchip/clk_rk3399.c:53:29: warning: 'cpll_init_cfg' defined but not used [-Wunused-const-variable=]
     static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
                                 ^~~~~~~~~~~~~
    drivers/clk/rockchip/clk_rk3399.c:52:29: warning: 'gpll_init_cfg' defined but not used [-Wunused-const-variable=]
     static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
                                 ^~~~~~~~~~~~~
* for the non-SPL build:
    drivers/clk/rockchip/clk_rk3399.c:54:29: warning: 'ppll_init_cfg' defined but not used [-Wunused-const-variable=]
     static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
                                 ^~~~~~~~~~~~~

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Due to differences in the code paths for SPL and non-SPL, some static
constant structures remain unused in each build variant. This raises
warnings with recent GCC versions (we currently use GCC-6.3).

The warnings addressed in this commit (by matching #if conditions for
the variable definition with their uses) are:

* for the SPL build:
    drivers/clk/rockchip/clk_rk3399.c:53:29: warning: 'cpll_init_cfg' defined but not used [-Wunused-const-variable=]
     static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
                                 ^~~~~~~~~~~~~
    drivers/clk/rockchip/clk_rk3399.c:52:29: warning: 'gpll_init_cfg' defined but not used [-Wunused-const-variable=]
     static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
                                 ^~~~~~~~~~~~~
* for the non-SPL build:
    drivers/clk/rockchip/clk_rk3399.c:54:29: warning: 'ppll_init_cfg' defined but not used [-Wunused-const-variable=]
     static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
                                 ^~~~~~~~~~~~~

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: clk: rk3188: Allow configuration of the armclk</title>
<updated>2017-04-05T02:01:57+00:00</updated>
<author>
<name>Heiko Stübner</name>
<email>heiko@sntech.de</email>
</author>
<published>2017-03-20T11:40:32+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f785357073be1563b2f668a1b4bb5847bfaa96f9'/>
<id>f785357073be1563b2f668a1b4bb5847bfaa96f9</id>
<content type='text'>
The armclk starts in slow mode (24MHz) on the rk3188, which makes the whole
startup take a lot of time. We therefore want to at least move to the safe
600MHz value we can use with default pmic settings.
This is also the freqency the proprietary sdram-init leaves the cpu at.

For boards that have pmic control later in u-boot, we also add the option
to set the maximum frequency of 1.6GHz, if they so desire.

Signed-off-by: Heiko Stuebner &lt;heiko@sntech.de&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The armclk starts in slow mode (24MHz) on the rk3188, which makes the whole
startup take a lot of time. We therefore want to at least move to the safe
600MHz value we can use with default pmic settings.
This is also the freqency the proprietary sdram-init leaves the cpu at.

For boards that have pmic control later in u-boot, we also add the option
to set the maximum frequency of 1.6GHz, if they so desire.

Signed-off-by: Heiko Stuebner &lt;heiko@sntech.de&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-rockchip</title>
<updated>2017-03-17T18:15:17+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-03-17T13:11:12+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f9515756b6d76cde99b385dda905dfb20d31ea48'/>
<id>f9515756b6d76cde99b385dda905dfb20d31ea48</id>
<content type='text'>
This includes support for rk3188 from Heiko Stübner and and rk3328 from
Kever Yang.  Also included is SPL support for rk3399 and a fix for
rk3288 to get it booting again (spl_early_init()).
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This includes support for rk3188 from Heiko Stübner and and rk3328 from
Kever Yang.  Also included is SPL support for rk3399 and a fix for
rk3288 to get it booting again (spl_early_init()).
</pre>
</div>
</content>
</entry>
<entry>
<title>stm32f7: clk: remove usart1 clock enable from board init</title>
<updated>2017-03-17T18:15:14+00:00</updated>
<author>
<name>Vikas Manocha</name>
<email>vikas.manocha@st.com</email>
</author>
<published>2017-02-12T18:25:48+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b5be8f5ea8d9b0ffc46f818ce0cb38cd16f99e4d'/>
<id>b5be8f5ea8d9b0ffc46f818ce0cb38cd16f99e4d</id>
<content type='text'>
Before clock driver availability it was required to enable usart1 clock
for serial init but now with clock driver is taking care of usart1 clock.

Signed-off-by: Vikas Manocha &lt;vikas.manocha@st.com&gt;
</content>
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<pre>
Before clock driver availability it was required to enable usart1 clock
for serial init but now with clock driver is taking care of usart1 clock.

Signed-off-by: Vikas Manocha &lt;vikas.manocha@st.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: stm32f7: add clock driver for stm32f7 family</title>
<updated>2017-03-17T18:15:12+00:00</updated>
<author>
<name>Vikas Manocha</name>
<email>vikas.manocha@st.com</email>
</author>
<published>2017-02-12T18:25:45+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=712f99a5ddc404f8c6eac481cfe19f82ca2ecb4f'/>
<id>712f99a5ddc404f8c6eac481cfe19f82ca2ecb4f</id>
<content type='text'>
add basic clock driver support for stm32f7 to enable clocks required by
the peripherals.

Signed-off-by: Vikas Manocha &lt;vikas.manocha@st.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
add basic clock driver support for stm32f7 to enable clocks required by
the peripherals.

Signed-off-by: Vikas Manocha &lt;vikas.manocha@st.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: rk3328: add clock driver</title>
<updated>2017-03-16T22:03:46+00:00</updated>
<author>
<name>Kever Yang</name>
<email>kever.yang@rock-chips.com</email>
</author>
<published>2017-02-23T07:37:52+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=41793000d77172a7472aad256049473c00e29dc5'/>
<id>41793000d77172a7472aad256049473c00e29dc5</id>
<content type='text'>
Add rk3328 clock driver and cru structure definition.

Signed-off-by: William Zhang &lt;william.zhang@rock-chips.com&gt;
Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add rk3328 clock driver and cru structure definition.

Signed-off-by: William Zhang &lt;william.zhang@rock-chips.com&gt;
Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: rk3188: Add clock driver</title>
<updated>2017-03-16T22:03:45+00:00</updated>
<author>
<name>Heiko Stübner</name>
<email>heiko@sntech.de</email>
</author>
<published>2017-02-18T18:46:34+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=dcdd32788a03bd5e6dde79384eef0217a8e14b71'/>
<id>dcdd32788a03bd5e6dde79384eef0217a8e14b71</id>
<content type='text'>
Add a driver for setting up and modifying the various PLLs and peripheral
clocks on the RK3188.

Signed-off-by: Heiko Stuebner &lt;heiko@sntech.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add a driver for setting up and modifying the various PLLs and peripheral
clocks on the RK3188.

Signed-off-by: Heiko Stuebner &lt;heiko@sntech.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: clk: rk3288: limit gpll and cpll init to SPL build</title>
<updated>2017-03-16T22:03:44+00:00</updated>
<author>
<name>Heiko Stübner</name>
<email>heiko@sntech.de</email>
</author>
<published>2017-02-18T18:46:22+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6496498a626dbde4d0ed96406e4efee9ff2ab0c0'/>
<id>6496498a626dbde4d0ed96406e4efee9ff2ab0c0</id>
<content type='text'>
The gpll and cpll init values are only used in rk_clk_init in the SPL
and therefore produce compile time warnings in regular uboot builds.
Fix that with an #ifdef.

Signed-off-by: Heiko Stuebner &lt;heiko@sntech.de&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Added rockchip tag:
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
The gpll and cpll init values are only used in rk_clk_init in the SPL
and therefore produce compile time warnings in regular uboot builds.
Fix that with an #ifdef.

Signed-off-by: Heiko Stuebner &lt;heiko@sntech.de&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Added rockchip tag:
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
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