u-boot.git/drivers/clk, branch v2017.07Unnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/u-boot.git/atom/drivers/clk?h=v2017.072017-06-24T22:18:41ZMerge git://git.denx.de/u-boot-uniphier2017-06-24T22:18:41ZTom Rinitrini@konsulko.com2017-06-24T22:18:41Zurn:sha1:524b42bc2c6ae0a3d1d73a83de59346e4b3becd7
- fix sparse warnings
- sync DT with Linux
- add new board support (LD11/LD20 global)
ARM: uniphier: fix various sparse warnings2017-06-24T21:06:09ZMasahiro Yamadayamada.masahiro@socionext.com2017-06-22T07:42:04Zurn:sha1:1d21e1b97c39d7a6e40a22d3a4153231cf4296af
Fix warnings reported by sparse:
- ... was not declared. Should it be static?"
- cast to restricted __be32
While fixing those, the type conflict of cci500_init() was found.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Merge branch 'master' of git://git.denx.de/u-boot-rockchip2017-06-23T15:02:21ZTom Rinitrini@konsulko.com2017-06-23T15:02:21Zurn:sha1:7df4ff2c2689a6d3c16eb0c3cce098fcac622b0crockchip: clk: rk3036: correct setting for pll integer mode2017-06-23T14:40:23ZKever Yangkever.yang@rock-chips.com2017-06-13T02:03:11Zurn:sha1:6a464d9cab63f5317bc914e2de52a4de98377743
According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll
integer mode, while the '0' means the frac mode.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
clk_rv1108.c: Fix unused variable warning2017-06-23T14:38:05ZTom Rinitrini@konsulko.com2017-06-16T17:06:28Zurn:sha1:872faf5d1382a265be42ecaaa84abce5907811ea
The variables gpll_init_cfg and apll_init_cfg are unused in this file,
remove them.
Cc: Simon Glass <sjg@chromium.org>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
rockchip: Init clocks again when chain-loading2017-06-09T19:45:33ZSimon Glasssjg@chromium.org2017-05-31T23:57:32Zurn:sha1:d3cb46aa8c41e85b07ccf494ca90f3a7fe19373d
Detect with a previous boot loader has already set up the clocks and set
them up again so that U-Boot gets what it expects.
Signed-off-by: Simon Glass <sjg@chromium.org>
rockchip: rk3288: Convert clock driver to use shifted masks2017-06-09T19:45:33ZSimon Glasssjg@chromium.org2017-05-31T23:57:31Zurn:sha1:b223c1aeade5b29c13347354edd1ce4e66f60b7f
Shifted masks are the standard approach with rockchip since it allows
use of the mask without shifting it each time. Update the definitions and
the driver to match.
Signed-off-by: Simon Glass <sjg@chromium.org>
rockchip: clk: Add rv1108 clock driver2017-06-07T13:29:25ZAndy Yanandy.yan@rock-chips.com2017-06-01T10:00:36Zurn:sha1:bae2f282a96e400a2bbcc8a545598289f36e1c32
Add clock driver support for Rockchip rv1108 soc
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
rockchip: clock: rk3036: some fix according TRM2017-06-07T13:29:20ZKever Yangkever.yang@rock-chips.com2017-05-15T12:52:16Zurn:sha1:1960b0103420a74ae5b154ed8684785036e2235b
- hclk/pclk_div range　should use '<=' instead of '<'
- use GPLL for pd_bus clock source
- pd_bus HCLK/PCLK clock rate should not bigger than ACLK
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
rockchip: rk3036: clean mask definition for cru reg2017-06-07T13:29:20ZKever Yangkever.yang@rock-chips.com2017-05-15T12:52:15Zurn:sha1:37943aaeea55011d48a0a492838c50111ba2a37e
Embeded the shift in mask MACRO definition in cru header file
and clock driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>