u-boot.git/drivers/clk, branch v2017.09

clk: uniphier: add System clock support

2017-08-30T00:07:04+00:00

Support system clocks for LD4, Pro4, sLD8, Pro5, PXs2/LD6b, LD11, LD20.

Signed-off-by: Masahiro Yamada

clk: rmobile: Split R8A7795 and R8A7796 core clock tables

2017-08-25T22:04:49+00:00

The R8A7795 and R8A7796 tables use different constants to identify
clock in DT, so split the tables and use the correct constants on
R8A7795. This fixes UART clock misconfiguration on R8A7795.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
Signed-off-by: Nobuhiro Iwamatsu

ARM: uniphier: remove sLD3 SoC support

2017-08-20T14:05:39+00:00

This SoC is too old.  It is difficult to maintain any longer.

Signed-off-by: Masahiro Yamada

clk: uniphier: fix unmet direct dependencies warning

2017-08-20T14:05:39+00:00

Since commit f0776a551764 ("spl: dm: Kconfig: SPL_CLK depends on
SPL_DM"), the following warning is displayed:

  $ make uniphier_v8_defconfig
  warning: (ARCH_ZYNQ && ARCH_ZYNQMP && STM32F7 && CLK_UNIPHIER) selects
  SPL_CLK which has unmet direct dependencies (CLK && SPL_DM)

While I am here, I am removing the prompt to make it user-unconfigurable
option so that "select CLK_UNIPHIER" can be omitted.

Signed-off-by: Masahiro Yamada

rockchip: clk: remove RATE_TO_DIV

2017-08-13T15:15:09+00:00

Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.

Signed-off-by: Kever Yang 
Reviewed-by: Philipp Tomsich 
Acked-by: Philipp Tomsich

rockchip: clk: update dwmmc clock div

2017-08-13T15:15:09+00:00

dwmmc controller has default internal divider by 2,
and we always provide double of the clock rate request by
dwmmc controller. Sync code for all Rockchip SoC with:
4055b46 rockchip: clk: rk3288: fix mmc clock setting

Signed-off-by: Kever Yang 
Reviewed-by: Philipp Tomsich 
Acked-by: Philipp Tomsich 
[fixup for 'missing DIV_ROUND_UP' conflict for clk_rk3288.c:]
Signed-off-by: Philipp Tomsich

rockchip: clk: rk3368: add support for configuring the SPI clocks

2017-08-13T15:12:33+00:00

As SPI support may be useful in the boot-flow, this adds support for
configuring the SPI controller's clocks in the RK3368 clock driver.

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass

rockchip: clk: rk3368: mark 'priv' __maybe_unused in rk3368_clk_set_rate()

2017-08-13T15:12:32+00:00

With the clock support in rk3368_clk_set_rate() conditionalized on
various feature definitions, 'priv' can remain unused (e.g. in the
SPL build when only MMC is enabled).

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass

rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock

2017-08-13T15:12:32+00:00

To enable the GMAC on the RK3368, we need to set up the clocking
appropriately to generate a tx_clk for the MAC.

This adds an implementation that implements the use of the <&ext_gmac>
clock (i.e. an external 125MHz clock for RGMII provided by the PHY).
This is the clock setup used by the boards currently supported by
U-Boot (i.e. Geekbox, Sheep and RK3368-uQ7).

This includes the change from commit
 - rockchip: clk: rk3368: define GMAC_MUX_SEL_EXTCLK

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass

rockchip: clk: rk3368: support configuring the DRAM PLL (from TPL)

2017-08-13T15:12:32+00:00

As part of the DRAM initialisation process (running as part of the TPL
stage) on the RK3368, we need to set up the DRAM PLL.

This implements support for configuring the PLL to for 1200, 1332 or
1600 MHz (i.e. for DDR3-1200, DDR3-1333, DDR3-1600 operating modes).

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass