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<title>u-boot.git/drivers/clk, branch v2017.11</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>stm32: fix STMicroelectronics copyright</title>
<updated>2017-11-06T14:51:01+00:00</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@st.com</email>
</author>
<published>2017-10-23T07:53:58+00:00</published>
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<id>3bc599c956f84999299ae277af11379df4cb8e3c</id>
<content type='text'>
Uniformize STMicroelectronics copyrights headers for STM32
related code.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
</content>
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<pre>
Uniformize STMicroelectronics copyrights headers for STM32
related code.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: rk3399: init CPU clock when rkclk_init()</title>
<updated>2017-11-01T10:21:32+00:00</updated>
<author>
<name>Kever Yang</name>
<email>kever.yang@rock-chips.com</email>
</author>
<published>2017-10-12T07:27:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9f636a249c126b74e673e6d9592215f9b06c4f0b'/>
<id>9f636a249c126b74e673e6d9592215f9b06c4f0b</id>
<content type='text'>
Init the CPU and its buses to speed up the boot time.
Move rkclk_init() to a place after rk3399_configure_cpu has defined
at the same time, or else there will be a warning.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Acked-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
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<pre>
Init the CPU and its buses to speed up the boot time.
Move rkclk_init() to a place after rk3399_configure_cpu has defined
at the same time, or else there will be a warning.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Acked-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: clk: fix PWR_CR3 register's bit 2 name</title>
<updated>2017-10-16T13:42:51+00:00</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@st.com</email>
</author>
<published>2017-10-09T09:41:24+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6c1bf6c442612135bbabe0112060c8bae86fdfbc'/>
<id>6c1bf6c442612135bbabe0112060c8bae86fdfbc</id>
<content type='text'>
Fix bit 2 name of PWR_CR3 register to match with the
last STM32H7 reference manual available here :

http://www.st.com/content/st_com/en/support/resources/
resource-selector.html?querycriteria=productId=SS1951$$
resourceCategory=technical_literature$$resourceType=reference_manual

Update also comment about voltage scaling 1 values

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Reviewed-by: Vikas Manocha &lt;vikas.manocha@st.com&gt;
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<pre>
Fix bit 2 name of PWR_CR3 register to match with the
last STM32H7 reference manual available here :

http://www.st.com/content/st_com/en/support/resources/
resource-selector.html?querycriteria=productId=SS1951$$
resourceCategory=technical_literature$$resourceType=reference_manual

Update also comment about voltage scaling 1 values

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Reviewed-by: Vikas Manocha &lt;vikas.manocha@st.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: clk: remove CLK() macro for clk_stm32h7</title>
<updated>2017-10-16T13:42:51+00:00</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@st.com</email>
</author>
<published>2017-10-09T09:41:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1b4ce69dc2f92af719ae60891559102048c38c84'/>
<id>1b4ce69dc2f92af719ae60891559102048c38c84</id>
<content type='text'>
CLK() macro is a residue of a previously reworked patch,
remove it.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Reviewed-by: Vikas Manocha &lt;vikas.manocha@st.com&gt;
</content>
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<pre>
CLK() macro is a residue of a previously reworked patch,
remove it.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Reviewed-by: Vikas Manocha &lt;vikas.manocha@st.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: uniphier: add NAND controller clock</title>
<updated>2017-10-15T13:32:25+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2017-10-13T17:21:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7d9927c89539aa1be80b7f7ceee7cf7c001a0d1f'/>
<id>7d9927c89539aa1be80b7f7ceee7cf7c001a0d1f</id>
<content type='text'>
This allows the NAND driver to enable clock and get its clock rate.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
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<pre>
This allows the NAND driver to enable clock and get its clock rate.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>clk: uniphier: add PXs3 clock data</title>
<updated>2017-10-15T13:32:25+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2017-10-13T10:22:00+00:00</published>
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<id>ab05406e73284e194ceffb956d9bcd957b6c8c00</id>
<content type='text'>
Add basic clock data for Socionext's new SoC PXs3.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
<content type='xhtml'>
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<pre>
Add basic clock data for Socionext's new SoC PXs3.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: uniphier: rework for better clock tree structure</title>
<updated>2017-10-15T13:32:25+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2017-10-13T10:21:59+00:00</published>
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<id>d6c7ee7d281e1bace42d5981b35a98322b994bc1</id>
<content type='text'>
U-Boot does not support fancy clock tree structures like the Linux
common clock framework.  Implement a simple clock tree model at the
driver level.  With this, the clock data will be simplified.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
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<pre>
U-Boot does not support fancy clock tree structures like the Linux
common clock framework.  Implement a simple clock tree model at the
driver level.  With this, the clock data will be simplified.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'rmobile' of git://git.denx.de/u-boot-sh</title>
<updated>2017-10-11T00:14:38+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-10-11T00:14:38+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2ee87b0c1a5439e4ad6467cb8d5e8fb58922ca4b'/>
<id>2ee87b0c1a5439e4ad6467cb8d5e8fb58922ca4b</id>
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<pre>
</pre>
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</entry>
<entry>
<title>treewide: replace with error() with pr_err()</title>
<updated>2017-10-04T15:59:44+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2017-09-16T05:10:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9b643e312d528f291966c1f30b0d90bf3b1d43dc'/>
<id>9b643e312d528f291966c1f30b0d90bf3b1d43dc</id>
<content type='text'>
U-Boot widely uses error() as a bit noisier variant of printf().

This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:

  # define __compiletime_error(message) __attribute__((error(message)))

This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux.  (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)

Let's convert error() into now treewide-available pr_err().

Done with the help of Coccinelle, excluing tools/ directory.

The semantic patch I used is as follows:

// &lt;smpl&gt;
@@@@
-error
+pr_err
 (...)
// &lt;/smpl&gt;

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
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<pre>
U-Boot widely uses error() as a bit noisier variant of printf().

This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:

  # define __compiletime_error(message) __attribute__((error(message)))

This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux.  (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)

Let's convert error() into now treewide-available pr_err().

Done with the help of Coccinelle, excluing tools/ directory.

The semantic patch I used is as follows:

// &lt;smpl&gt;
@@@@
-error
+pr_err
 (...)
// &lt;/smpl&gt;

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: rk322x: fix pd_bus hclk/pclk</title>
<updated>2017-09-30T22:33:32+00:00</updated>
<author>
<name>Kever Yang</name>
<email>kever.yang@rock-chips.com</email>
</author>
<published>2017-09-28T10:24:03+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f3f6591ca39325f34ef3ec3600be2e493b3a0327'/>
<id>f3f6591ca39325f34ef3ec3600be2e493b3a0327</id>
<content type='text'>
The pd_bus hclk/pclk source is pd_bus aclk, not the PLL.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Acked-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
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<pre>
The pd_bus hclk/pclk source is pd_bus aclk, not the PLL.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Acked-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</pre>
</div>
</content>
</entry>
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