<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/clk, branch v2018.03-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/clk?h=v2018.03-rc2</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/clk?h=v2018.03-rc2'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2018-01-29T17:48:33Z</updated>
<entry>
<title>clk: clk_stm32: Add .set_rate callback</title>
<updated>2018-01-29T17:48:33Z</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@st.com</email>
</author>
<published>2018-01-29T17:14:14Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=05e23dd489685c99be4ff4fe1c41543a3688dceb'/>
<id>urn:sha1:05e23dd489685c99be4ff4fe1c41543a3688dceb</id>
<content type='text'>
Since 'commit f4fcba5c5baa ("clk: implement clk_set_defaults()")'
STM32F4 family board can't boot.

Above patch calls clk_set_rate() for all nodes with assigned-clock-rates
property. Clock driver for STM32F family doesn't implement .set_rate
callback which make clk_set_defaults() exit on error and prevent board
to boot.

Fixes: f4fcba5c5baa ("clk: implement clk_set_defaults()")
Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-rockchip</title>
<updated>2018-01-28T18:56:19Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-01-28T18:56:19Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f2ee91501892d3280a4c58093ad3a18dccd0b562'/>
<id>urn:sha1:f2ee91501892d3280a4c58093ad3a18dccd0b562</id>
<content type='text'>
</content>
</entry>
<entry>
<title>rockchip: clk: guard set_parent implementations against OF_PLATDATA</title>
<updated>2018-01-28T16:12:39Z</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2018-01-25T14:27:10Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=75b381aae8dd5fbc3c6b3f453dc3ca9ce3c94ab4'/>
<id>urn:sha1:75b381aae8dd5fbc3c6b3f453dc3ca9ce3c94ab4</id>
<content type='text'>
The set_parent implementations do not make sense when OF_PLATDATA is
enabled.  We guard these against OF_PLATDATA and don't populate the
set_parent-op when this is the case.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
</entry>
<entry>
<title>clk: rockchip: clk_rk3368: Implement "assign-clock-parent"</title>
<updated>2018-01-28T16:12:39Z</updated>
<author>
<name>David Wu</name>
<email>david.wu@rock-chips.com</email>
</author>
<published>2018-01-13T06:07:04Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=64a12202ed113c4696c0f4b6c3d6a35d97383851'/>
<id>urn:sha1:64a12202ed113c4696c0f4b6c3d6a35d97383851</id>
<content type='text'>
Implement the setting parent for gmac clock, and add internal
pll div set for mac clk.

Signed-off-by: David Wu &lt;david.wu@rock-chips.com&gt;
Acked-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
</entry>
<entry>
<title>clk: rockchip: clk_rk3288: Implement "assign-clock-parent" and "assign-clock-rate"</title>
<updated>2018-01-28T16:12:39Z</updated>
<author>
<name>David Wu</name>
<email>david.wu@rock-chips.com</email>
</author>
<published>2018-01-13T06:06:33Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=01c60eafbbf613f8b29fb317f7c52be932d303d1'/>
<id>urn:sha1:01c60eafbbf613f8b29fb317f7c52be932d303d1</id>
<content type='text'>
The RK3288 CRU-node assigns rates to a number of clocks that are not
implemented in the RK3288 clock-driver (but which have been
sufficiently initialised from rkclk_init()): for these clocks, we
implement the gmac clock set parent, but simply ignore the
others' set_rate() operation and return 0 to signal success.

Signed-off-by: David Wu &lt;david.wu@rock-chips.com&gt;
Acked-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
</entry>
<entry>
<title>clk: rockchip: Add rk322x gamc clock support</title>
<updated>2018-01-28T16:12:38Z</updated>
<author>
<name>David Wu</name>
<email>david.wu@rock-chips.com</email>
</author>
<published>2018-01-13T06:05:12Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5bb616c6e2ba3ff4098b882bb0bcd7e0000376dd'/>
<id>urn:sha1:5bb616c6e2ba3ff4098b882bb0bcd7e0000376dd</id>
<content type='text'>
Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface.

Signed-off-by: David Wu &lt;david.wu@rock-chips.com&gt;
Acked-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
</entry>
<entry>
<title>clk: rockchip: Add rk3328 gamc clock support</title>
<updated>2018-01-28T16:12:37Z</updated>
<author>
<name>David Wu</name>
<email>david.wu@rock-chips.com</email>
</author>
<published>2018-01-13T06:02:36Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7cd4ebab2bc425b027dc91872b1feb766e9bc9ff'/>
<id>urn:sha1:7cd4ebab2bc425b027dc91872b1feb766e9bc9ff</id>
<content type='text'>
The rk3328 soc has two gmac controllers, one is gmac2io,
the other is gmac2phy. We use the gmac2io rgmii interface
for 1000M phy here.

Signed-off-by: David Wu &lt;david.wu@rock-chips.com&gt;
Acked-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
</entry>
<entry>
<title>rockchip: clk: rk3399: accept all assigned-clocks from the 'cru'-node</title>
<updated>2018-01-28T16:12:36Z</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2018-01-08T13:00:27Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d2f1f1abafbedd3580334f2564bfea918e49522d'/>
<id>urn:sha1:d2f1f1abafbedd3580334f2564bfea918e49522d</id>
<content type='text'>
The RK3399 CRU-node assigns rates to a number of clocks that are not
implemented in the RK3399 clock-driver (but which have been
sufficiently initialised from rkclk_init()): for these clocks, we
simply ignore the set_rate() operation and return 0 to signal success.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Tested-by: David Wu &lt;david.wu@rock-chips.com&gt;

Series-changes: 2
- Fixed David's email address.
</content>
</entry>
<entry>
<title>clk: implement clk_set_defaults()</title>
<updated>2018-01-28T16:12:36Z</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2018-01-08T12:59:18Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f4fcba5c5baaaa9d477d753f97124efdb8e45893'/>
<id>urn:sha1:f4fcba5c5baaaa9d477d753f97124efdb8e45893</id>
<content type='text'>
Linux uses the properties 'assigned-clocks', 'assigned-clock-parents'
and 'assigned-clock-rates' to configure the clock subsystem for use
with various peripheral nodes.

This implements clk_set_defaults() and hooks it up with the general
device probibin in drivers/core/device.c: when a new device is probed,
clk_set_defaults() will be called for it and will process the
properties mentioned above.

Note that this functionality is designed to fail gracefully (i.e. if a
clock-driver does not implement set_parent(), we simply accept this
and ignore the error) as not to break existing board-support.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Tested-by: David Wu &lt;david.wu@rock-chips.com&gt;

Series-changes: 2
- Fixed David's email address.

Series-version: 2

Cover-letter:
clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates

For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC),
the parent-clock needs to be set via the DTS.  This adds the required
plumbing and implements the GMAC case for the RK3399.
END
</content>
</entry>
<entry>
<title>rockchip: clk: rk3399: implement set_parent() operation</title>
<updated>2018-01-28T16:12:36Z</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2018-01-08T12:11:01Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a45f17e8b9f91628936349ef40a06d10dc9c08ae'/>
<id>urn:sha1:a45f17e8b9f91628936349ef40a06d10dc9c08ae</id>
<content type='text'>
This implements the (newly added) set_parent() operation for the
RK3399 with a focus on allowing the RGMII clock parent to be
configured via the assigned-clock-parents property of the GMAC node.

This implementation supports only the GMAC (in fact only the RGMII
clock parent) and allows to set this clock's parent either to the
internal SCLK_GMAC or to an external clock input (identifiable by it
providing a 'clock-output-name' of "gmac_clkin").

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Tested-by: David Wu &lt;david.wu@rock-chips.com&gt;

Series-changes: 2
- Fixed David's email address.
</content>
</entry>
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