u-boot.git/drivers/clk, branch v2018.05-rc2

clk: renesas: Minor clean up of the R8A7790 clock driver

2018-04-13T21:41:44Z

The initconst is not used in U-Boot, drop it. The r8a7790_crit_mod_clks is also not used in U-Boot, so drop it too. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu

clk: add sandbox test for bulk API

2018-04-10T19:18:56Z

This patch adds the bulk clock API tests for the sandbox test suite. It's very similar to the main test but only uses the _bulk() API and checks if the clocks are correctly enabled/disabled. Signed-off-by: Neil Armstrong Reviewed-by: Simon Glass

clk: Add get/enable/disable/release for a bulk of clocks

2018-04-10T15:52:16Z

This patch adds a "bulk" API to the clock API in order to get/enable/disable /release a group of clocks associated with a device. This bulk API will avoid adding a copy of the same code to manage a group of clocks in drivers. Signed-off-by: Neil Armstrong Reviewed-by: Simon Glass

clk: zynqmp: Add new compatible string for clock driver

2018-04-09T10:14:50Z

New and old clk drivers are sharing IDs and descriptions. Signed-off-by: Michal Simek

clock: stm32mp1: add stgen clock source change support

2018-04-07T00:45:28Z

The STGEN is the clock source for the Cortex A7 arch timer. So after modification of its frequency, CP15 cntfreq is updated and a new timer init is performed. Signed-off-by: Patrick Delaunay

rockchip: clk: rk3188: update dpll settings to make EMAC work

2018-03-28T21:44:59Z

The patch set dpll settings for 300MHz to values used by binary blob[1]. With new values dpll still generate 300MHz clock, but EMAC work. Probably with new values dpll generate more stable clock. dpll on rk3188 provide clocks to DDR and EMAC. With current dpll settings EMAC doesn't work on radxa rock. EMAC sends packets to network, but it doesn't receive anything. ifconfig shows a lot of framing errors. [1] https://github.com/linux-rockchip/u-boot-rockchip/blob/u-boot-rk3288/ tools/rk_tools/3188_LPDDR2_300MHz_DDR3_300MHz_20130830.bin Signed-off-by: Alexander Kochetkov Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich

arm64: zynqmp: Print the value of pl clocks and wdt clock using clk dump

2018-03-23T08:34:44Z

This patch print pl clocks (pl0...pl3) and watchdog clock using clk dump. Signed-off-by: Vipul Kumar Signed-off-by: Michal Simek

clk: zynq: Show watchdog clock rate properly

2018-03-23T08:34:43Z

watchdog clock is also connected to cpu 1X clocksource. Zynq> clk dump ... Before: swdt 4294967290 After: swdt 111111110 Signed-off-by: Michal Simek

clk: stm32mp1: add clock tree initialization

2018-03-19T20:14:22Z

add binding and code for clock tree initialization from device tree Signed-off-by: Patrick Delaunay

clk: add driver for stm32mp1

2018-03-19T20:14:22Z

add RCC clock driver for STMP32MP157 - base on driver model = UCLASS_CLK - support ops to enable, disable and get rate of all SOC clock needed by U-Boot Signed-off-by: Patrick Delaunay