u-boot.git/drivers/clk, branch v2018.07

clk: add Amlogic meson clock driver

2018-06-19T11:31:47+00:00

Introduce a basic clock driver for Amlogic Meson SoCs which supports
enabling/disabling clock gates and getting their frequency.

Signed-off-by: Beniamino Galvani 
Signed-off-by: Neil Armstrong

clk: rmobile: Add R8A77995 RPC clock

2018-06-14T11:36:33+00:00

Add missing RPC entry into the R8A77995 clock driver tables.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu

clk: rmobile: Add R8A77990 RPC clock

2018-06-14T11:36:33+00:00

Add missing RPC entry into the R8A77990 clock driver tables.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu

Merge branch 'master' of git://git.denx.de/u-boot-sh

2018-06-02T20:58:27+00:00

clk: bcm6345: convert to use live dt

2018-06-01T13:56:02+00:00

Signed-off-by: Álvaro Fernández Rojas 
Reviewed-by: Simon Glass 
Reviewed-by: Daniel Schwierzeck

clk: renesas: Add R8A77990 E3 clock tables

2018-06-01T07:47:01+00:00

Add clock tables for R8A77990 E3 SoC .

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu

clk: renesas: Add PE clock handling

2018-06-01T07:42:13+00:00

The PE clock have two parents, add support for picking the correct
one and deriving the clock from it.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu

clk: renesas: Add PLL1 and PLL3 dividers

2018-06-01T07:42:13+00:00

Add and use the PLL1 and PLL3 dividers.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu

clk: renesas: Pass clock rate around as 64bit number internally

2018-06-01T07:42:13+00:00

The PLL rate could be in the GHz range, which could overflow a 32bit
data type. Since the hardware is 64bit anyway, pass the clock rates
as 64bit number internally to avoid this.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu

clk: renesas: Fix swapped arguments in debug message

2018-06-01T07:42:13+00:00

The mul and div arguments were reported in reverse order in the debug
message, swap them to fix this.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu