Add clock driver for the Arria10, which allows reading the clock
frequency from all the clock described in the DT. The driver also
allows enabling and disabling the clock. Reconfiguring frequency
is not supported thus far.

Since the DT bindings for the SoCFPGA clock are massively misdesigned
and the handoff DT adds additional incorrectly described entries to
the DT, the driver contains workarounds which attempt to rectify all
of those problems.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

In case the slow clock is not properly configured, the UTMI clock
cannot lock the PLL, because UPLLCOUNT will "wait X slow clock cycles".
In this case U-boot will loop indefinitely.
Added a timeout in this case, to start U-boot even if UTMI clock is
not enabled, so the user can use different media if needed, or investigate.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>

sourcing of sub directiory kconfig files are not in
proper order, so keep them in ascending order.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

The Assigned Clock parents and rates misses the fact that a "0" entry can
be passed to skip setting a parent or rate of an assigned clock as
described in the Linux clock bindings at [1].

This patch simply skips the clock reparenting if the DT parsing returns
-ENOENT and the clock rate setting if "0" is passed as clock rate.

[1] https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/clock/clock-bindings.txt#L135

Fixes: f4fcba5c5baa "clk: implement clk_set_defaults()"
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Add clk_valid() to check for optional clocks are valid.
Call clk_valid() in test/dm/clk.c and add relevant test routine to
sandbox clk tests.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

HSE and LSE bypass shall support both analog and digital signals.
This patch add a way to select digital bypas case in the device tree
and set the associated bit DIGBYP in RCC_BDCR and RCC_OCEN register
during clock tree initialization.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

Add ADC clock gating, that may be used by STM32 ADC.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

Alignment with kernel clock driver

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>