u-boot.git/drivers/clk, branch v2018.09-rc1

stm32mp1: clk: support digital bypass

2018-07-20T19:55:07Z

HSE and LSE bypass shall support both analog and digital signals. This patch add a way to select digital bypas case in the device tree and set the associated bit DIGBYP in RCC_BDCR and RCC_OCEN register during clock tree initialization. Signed-off-by: Patrick Delaunay

stm32mp1: clk: add ADC clock gating

2018-07-20T19:55:07Z

Add ADC clock gating, that may be used by STM32 ADC. Signed-off-by: Fabrice Gasnier Signed-off-by: Patrick Delaunay

stm32mp1: clk: update Ethernet clock gating

2018-07-20T19:55:07Z

Alignment with kernel clock driver Signed-off-by: Patrice Chotard Signed-off-by: Patrick Delaunay

stm32mp1: clk: add LDTC and DSI clock support

2018-07-20T19:55:07Z

This patch add clk_enable/clk_disable/clk_get_rate support for - DSI_PX - LTDC_PX - DSI_K (only get rate) These clocks are needed for LTDC and DSI drivers with latest device tree. Signed-off-by: Patrick Delaunay

stm32mp1: clk: add common function pll_get_fvco

2018-07-20T19:55:06Z

the function compute the VCO PLL freq, used in - stm32mp1_read_pll_freq() - pll_set_rate() Signed-off-by: Patrick Delaunay # Conflicts: # drivers/clk/clk_stm32mp1.c

stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macro

2018-07-20T19:55:06Z

This patch define RCC_PLLNCFGR2_SHIFT to reuse it in the pll function for set rate. Signed-off-by: Patrick Delaunay Reviewed-by: Vikas Manocha

misc: stm32: Add STM32MP1 support

2018-07-20T19:55:05Z

Following next kernel rcc bindings, we must use a MFD RCC driver which is able to bind both clock and reset drivers. We can reuse and adapt RCC MFD driver already available for MCU SoCs (F4/F7/H7). Signed-off-by: Patrice Chotard Signed-off-by: Patrick Delaunay

clk: zynqmp: Fixed the same if/else part error reported by coverity

2018-07-19T08:49:53Z

This patch fixed the same if/else part error by adding the required source select on the basis of is_pre_src check. Signed-off-by: Vipul Kumar Signed-off-by: Michal Simek

clk: Add Actions Semi OWL clock support

2018-07-09T19:25:31Z

This commit adds Actions Semi OWL family base clock and S900 SoC specific clock support. For S900 peripheral clock support, only UART clock has been added for now. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Simon Glass

clk: add Amlogic meson clock driver

2018-06-19T11:31:47Z

Introduce a basic clock driver for Amlogic Meson SoCs which supports enabling/disabling clock gates and getting their frequency. Signed-off-by: Beniamino Galvani Signed-off-by: Neil Armstrong