u-boot.git/drivers/clk, branch v2018.09-rc2

clk: at91: utmi: add timeout for utmi lock

2018-08-13T18:03:57Z

In case the slow clock is not properly configured, the UTMI clock cannot lock the PLL, because UPLLCOUNT will "wait X slow clock cycles". In this case U-boot will loop indefinitely. Added a timeout in this case, to start U-boot even if UTMI clock is not enabled, so the user can use different media if needed, or investigate. Signed-off-by: Eugen Hristev

clk: clk_set_default: accept no-op skip fields

2018-08-04T18:50:10Z

The Assigned Clock parents and rates misses the fact that a "0" entry can be passed to skip setting a parent or rate of an assigned clock as described in the Linux clock bindings at [1]. This patch simply skips the clock reparenting if the DT parsing returns -ENOENT and the clock rate setting if "0" is passed as clock rate. [1] https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/clock/clock-bindings.txt#L135 Fixes: f4fcba5c5baa "clk: implement clk_set_defaults()" Signed-off-by: Neil Armstrong Reviewed-by: Simon Glass

clk: add clk_valid()

2018-08-03T23:53:10Z

Add clk_valid() to check for optional clocks are valid. Call clk_valid() in test/dm/clk.c and add relevant test routine to sandbox clk tests. Signed-off-by: Fabrice Gasnier Reviewed-by: Simon Glass

stm32mp1: clk: support digital bypass

2018-07-20T19:55:07Z

HSE and LSE bypass shall support both analog and digital signals. This patch add a way to select digital bypas case in the device tree and set the associated bit DIGBYP in RCC_BDCR and RCC_OCEN register during clock tree initialization. Signed-off-by: Patrick Delaunay

stm32mp1: clk: add ADC clock gating

2018-07-20T19:55:07Z

Add ADC clock gating, that may be used by STM32 ADC. Signed-off-by: Fabrice Gasnier Signed-off-by: Patrick Delaunay

stm32mp1: clk: update Ethernet clock gating

2018-07-20T19:55:07Z

Alignment with kernel clock driver Signed-off-by: Patrice Chotard Signed-off-by: Patrick Delaunay

stm32mp1: clk: add LDTC and DSI clock support

2018-07-20T19:55:07Z

This patch add clk_enable/clk_disable/clk_get_rate support for - DSI_PX - LTDC_PX - DSI_K (only get rate) These clocks are needed for LTDC and DSI drivers with latest device tree. Signed-off-by: Patrick Delaunay

stm32mp1: clk: add common function pll_get_fvco

2018-07-20T19:55:06Z

the function compute the VCO PLL freq, used in - stm32mp1_read_pll_freq() - pll_set_rate() Signed-off-by: Patrick Delaunay # Conflicts: # drivers/clk/clk_stm32mp1.c

stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macro

2018-07-20T19:55:06Z

This patch define RCC_PLLNCFGR2_SHIFT to reuse it in the pll function for set rate. Signed-off-by: Patrick Delaunay Reviewed-by: Vikas Manocha

misc: stm32: Add STM32MP1 support

2018-07-20T19:55:05Z

Following next kernel rcc bindings, we must use a MFD RCC driver which is able to bind both clock and reset drivers. We can reuse and adapt RCC MFD driver already available for MCU SoCs (F4/F7/H7). Signed-off-by: Patrice Chotard Signed-off-by: Patrick Delaunay