u-boot.git/drivers/clk, branch v2018.11-rc2

clk: Add support for Arm's Versatile Express OSC clock generators

2018-09-30T17:00:34Z

The Arm Versatile Express and Juno development boards contain an OSC clock generator that can be accessed through the Versatile Express config bus. The generators are quite often being controlled by some MCU and the config bus offers a uniform way of exposing them. Signed-off-by: Liviu Dudau Reviewed-by: Heiko Schocher

Merge git://git.denx.de/u-boot-marvell

2018-09-20T00:35:05Z

- Multiples updates to the turris boards / platform - Changes / enhancements to the Marvell PHY drivers, mainly to support the turris platform - Many fixes and enhancements to the pxa3xx NAND driver - Fixes for the UART boot mode in kwboot - Misc minor changes to other 32bit and 64bit boards

clk: armada-37xx-periph: Support changing clock parent and rate

2018-09-19T06:59:26Z

Add support for changing clock rate and parent clock for Armada 37xx peripheral clocks. Only clocks which can be disabled (.can_gate is true) can have parent or rate changed. This is needed so that Turris Mox can change SPI clock in device tree. Signed-off-by: Marek Behun Signed-off-by: Stefan Roese

clk: Add MPC83xx clock driver

2018-09-18T06:01:18Z

Add a clock driver for the MPC83xx architecture. Signed-off-by: Mario Six

clk: Introduce TI System Control Interface (TI SCI) clock driver

2018-09-11T12:32:55Z

Some TI Keystone 2 and K3 family of SoCs contain a system controller (like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and the Device Management and Security Controller on AM65x SoCs) that manage the low-level device control (like clocks, resets etc) for the various hardware modules present on the SoC. These device control operations are provided to the host processor OS through a communication protocol called the TI System Control Interface (TI SCI) protocol. This patch adds a clock driver that communicates to the system controller over the TI SCI protocol for performing clock management of various devices present on the SoC. Various clock functionality is achieved by the means of different TI SCI device operations provided by the TI SCI framework. This code is loosely based on the drivers/clk/keystone/sci-clk.c driver of the Linux kernel. Reviewed-by: Tom Rini Signed-off-by: Andreas Dannenberg Signed-off-by: Vignesh R Signed-off-by: Lokesh Vutla

clk: clk_meson: Add mux and div support for reparent and rate setting

2018-09-11T00:48:17Z

This patch adds support for : - Rate calculation through muxes and generic dividers - Basic gate setting propagation - Reparenting for muxes - Clock rate setting through generic dividers without reparenting Support is only added to the Composite VPU and VAPB clocks in order to support the Video Processing Unit Power Domain clock setup. Reviewed-by: Simon Glass Signed-off-by: Neil Armstrong

Merge branch 'master' of git://git.denx.de/u-boot-sunxi

2018-08-20T17:41:56Z

Merge branch 'master' of git://git.denx.de/u-boot-socfpga

2018-08-17T11:24:34Z

clk: socfpga: Add initial Arria10 clock driver

2018-08-13T20:35:42Z

Add clock driver for the Arria10, which allows reading the clock frequency from all the clock described in the DT. The driver also allows enabling and disabling the clock. Reconfiguring frequency is not supported thus far. Since the DT bindings for the SoCFPGA clock are massively misdesigned and the handoff DT adds additional incorrectly described entries to the DT, the driver contains workarounds which attempt to rectify all of those problems. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Ley Foon Tan

clk: at91: utmi: add timeout for utmi lock

2018-08-13T18:03:57Z

In case the slow clock is not properly configured, the UTMI clock cannot lock the PLL, because UPLLCOUNT will "wait X slow clock cycles". In this case U-boot will loop indefinitely. Added a timeout in this case, to start U-boot even if UTMI clock is not enabled, so the user can use different media if needed, or investigate. Signed-off-by: Eugen Hristev