u-boot.git/drivers/clk, branch v2019.01

clk: imx8: fix build warning

2019-01-09T16:03:29+00:00

When build clk driver in spl, met the warning:
"
drivers/clk/imx/clk-imx8.c:21:25: warning: ‘imx8_clk_names’ defined but not used [-Wunused-variable]
 static struct imx8_clks imx8_clk_names[] = {
                         ^~~~~~~~~~~~~~
"

Fix with wrapping the array with CONFIG_CMD_CLK.

Signed-off-by: Peng Fan

clk: uniphier: add NAND 200MHz clock

2018-12-29T02:38:38+00:00

The Denali NAND controller IP needs three clocks:

 - clk: controller core clock

 - clk_x: bus interface clock

 - ecc_clk: clock at which ECC circuitry is run

Currently, only the first one (50MHz) is provided.  The rest of the
two clock ports must be connected to the 200MHz clock line.  Add this.

Signed-off-by: Masahiro Yamada

clk: stm32: add hardware spinlock clock

2018-12-07T04:26:32+00:00

Add hardware spinlock in the list of the clocks.

Signed-off-by: Benjamin Gaignard 
Reviewed-by: Simon Glass 
Reviewed-by: Patrice Chotard

clk: Allow clock defaults to be set during re-reloc state for SPL only

2018-12-07T04:26:31+00:00

In commit e5e06b65ad65 ("clk: Allow clock defaults to be set also
during re-reloc state") the earlier guard against setting clock
defaults in pre-reloc state was removed.  While it is easy to filter
'assigned-clocks' properties for SPL using CONFIG_OF_SPL_REMOVE_PROPS,
no such mechanism exists for the pre-reloc stage of the full U-Boot.

With the default defconfig for the RK3399-Q7 (which filter the
'assigned-clocks' property for the DTS used by SPL anyway), this
caused a pause during startup of the full U-Boot stage that lasted for
almost 10s (due to the CPU not having been clocked up yet).

This reintroduces the guard from commit f4fcba5c5baa ("clk: Allow
clock defaults to be set also during re-reloc state") and extends it
to only apply outside of a TPL/SPL build: i.e. clk_set_defaults will
now run in pre-reloc state for SPL, but only after reloc for the full
U-Boot.

References: commit f4fcba5c5baa ("clk: implement clk_set_defaults()")
References: commit e5e06b65ad65 ("clk: Allow clock defaults to be set
also during re-reloc state")
Signed-off-by: Philipp Tomsich

Merge branch 'master' of git://git.denx.de/u-boot-sh

2018-12-03T22:51:45+00:00

- MMC fixes for R-Car Gen3

ARM: meson: Add regmap support for clock driver

2018-12-03T12:34:21+00:00

This patch modifies the meson clock driver to use syscon/regmap like
the Linux kernel does, as it is needed if we want to share the same
DTS files.

DTS files are synchronized from Linux 4.19.

Signed-off-by: Loic Devulder 
Acked-by: Neil Armstrong

clk: renesas: Allow reconfiguring SDHI clock on Gen3

2018-12-03T11:51:16+00:00

The SDHI clock must be configured differently for HS200/HS400/SDR104
modes. Add support for reconfiguring the SDHI clock settings into the
clock driver.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu

rockchip: rk3399: Initialize CPU B clock.

2018-11-30T20:56:45+00:00

This patch sets the PLL of CPU cluster B (BPLL) to 600 MHz.
This decreases the boot time of Linux 4.19 by about 8%.

The 600 MHz are inspired by the 600 MHz used for LPLL initialization
(came in with commit 9f636a249c1).

Tested on RK3399-Q7 on Haikou base board.

Signed-off-by: Christoph Muellner 
Reviewed-by: Philipp Tomsich

ARM: rockchip: rv1108: Sync clock with vendor tree

2018-11-30T20:56:44+00:00

Make adjustments to the rv1108 clock driver in order to align it
with the internal Rockchip version.

Signed-off-by: Otavio Salvador 
Reviewed-by: Philipp Tomsich

Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogic

2018-11-29T20:16:58+00:00

Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
- net: designware: add meson meson compatibles
- Amlogic Meson cleanup for AXG SoC support