u-boot.git/drivers/clk, branch v2019.04 Unnamed repository; edit this file 'description' to name the repository. clk: sunxi: a10: Add CLK_AHB_GMAC 2019-04-01T16:15:15+00:00 Jagan Teki jagan@amarulasolutions.com 2019-03-28T08:16:11+00:00 9d1e136734b80414c803301d69d4cd358001be93 CLK_AHB_GMAC was suppose to be part of previous commit "clk: sunxi: Implement A10 EMAC clocks" add it so-that we can get rid of sunxi_set_gate warning on boot message. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> 
CLK_AHB_GMAC was suppose to be part of previous commit
"clk: sunxi: Implement A10 EMAC clocks" add it so-that
we can get rid of sunxi_set_gate warning on boot message.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
clk: renesas: Add support for setting MMCIF clock divider on Gen2 2019-03-25T19:26:53+00:00 Marek Vasut marek.vasut+renesas@gmail.com 2019-03-18T05:04:02+00:00 3cb2849c76ddb7b4da6a164b8513e1309715d765 Add code for configuring the MMC0CKCR/MMC1CKCR on Gen2 platforms. This allows the MMCIF driver to set higher clock rate if desired. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 
Add code for configuring the MMC0CKCR/MMC1CKCR on Gen2 platforms.
This allows the MMCIF driver to set higher clock rate if desired.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
clk: renesas: Fix swapped div and mul in debug output on Gen2 2019-03-25T19:26:53+00:00 Marek Vasut marek.vasut+renesas@gmail.com 2019-03-18T04:38:08+00:00 4b135d54649eb79d5dfcd20feee82f6675c502c3 The $div and $mul values were swapped in the debug output, fix this. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 
The $div and $mul values were swapped in the debug output,
fix this.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
clk: renesas: Fix SDH clock divider decoding on Gen2 2019-03-25T19:26:53+00:00 Marek Vasut marek.vasut+renesas@gmail.com 2019-03-18T04:11:42+00:00 45b01b462feedaecb28c3407a438a245c73fe6d0 The gen2_clk_get_sdh_div() function is supposed to look up the $val value read out of the SDCKCR register in the supplied table and return the matching divider value. The current implementation was matching the value from SDCKCR on the divider value in the table, which is wrong. Fix this and rework the function a bit to make it more readable. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 
The gen2_clk_get_sdh_div() function is supposed to look up the
$val value read out of the SDCKCR register in the supplied table
and return the matching divider value. The current implementation
was matching the value from SDCKCR on the divider value in the
table, which is wrong. Fix this and rework the function a bit
to make it more readable.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
clk: sunxi: h3: Implement EPHY CLK and RESET 2019-03-09T07:46:35+00:00 Jagan Teki jagan@amarulasolutions.com 2019-02-27T18:56:59+00:00 aefc0b7a60b9147b79b7a735c045e28daba712f1 EPHY CLK and RESET is available in Allwinner H3 EMAC via mdio-mux node of internal PHY. Add the respective clock and reset reg and bits. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> 
EPHY CLK and RESET is available in Allwinner H3 EMAC
via mdio-mux node of internal PHY. Add the respective
clock and reset reg and bits.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
clk: sunxi: Implement EMAC, GMAC clocks, resets 2019-03-09T07:46:35+00:00 Jagan Teki jagan@amarulasolutions.com 2019-02-27T18:56:57+00:00 68620c9698f109c1f001f80d282138a5c67cabef - Implement EMAC, GMAC clocks via ccu_clk_gate for all supported Allwinner SoCs. - Implement EMAC, GMAC resets via ccu_reset for all supported Allwinner SoCs. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> 
- Implement EMAC, GMAC clocks via ccu_clk_gate for
  all supported Allwinner SoCs.
- Implement EMAC, GMAC resets via ccu_reset for all
  supported Allwinner SoCs.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
clk: sunxi: Implement A10 EMAC clocks 2019-03-09T07:46:35+00:00 Jagan Teki jagan@amarulasolutions.com 2019-02-27T18:56:49+00:00 3d83c4a1d4dd7ea230d5b5c073e503dca883e409 Implement EMAC clocks via ccu_clk_gate for Allwinner A10 SoC. Which would eventually used in sunxi_emac.c driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> 
Implement EMAC clocks via ccu_clk_gate for Allwinner A10 SoC.

Which would eventually used in sunxi_emac.c driver.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
clk: sunxi: Implement SPI clocks, resets 2019-03-04T12:38:56+00:00 Jagan Teki jagan@amarulasolutions.com 2019-02-27T14:32:06+00:00 82111469a5451adeb14413dc744c96f1bf13c758 - Implement SPI AHB, MOD clocks via ccu_clk_gate for all supported Allwinner SoCs - Implement SPI resets via ccu_reset for all supported Allwinner SoCs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> 
- Implement SPI AHB, MOD clocks via ccu_clk_gate for all
  supported Allwinner SoCs
- Implement SPI resets via ccu_reset for all supported
  Allwinner SoCs.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Merge branch 'master' of git://git.denx.de/u-boot-sh 2019-02-28T23:57:17+00:00 Tom Rini trini@konsulko.com 2019-02-28T23:57:17+00:00 35b05146f6a4853554b18ddc196d3bfcab5dd734 - Gen2/Gen3 fixes for warnings and sdhi 
- Gen2/Gen3 fixes for warnings and sdhi
clk: Add fixed-factor clock driver 2019-02-27T01:12:33+00:00 Anup Patel Anup.Patel@wdc.com 2019-02-25T08:14:55+00:00 b630d57d0ab45639eea02f2671c2aa0d023c89ac This patch adds fixed-factor clock driver which derives clock rate by dividing (div) and multiplying (mult) fixed factors to a parent clock. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
This patch adds fixed-factor clock driver which derives clock
rate by dividing (div) and multiplying (mult) fixed factors
to a parent clock.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Simon Glass <sjg@chromium.org>