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<title>u-boot.git/drivers/clk, branch v2020.01-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/clk?h=v2020.01-rc2</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/clk?h=v2020.01-rc2'/>
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<updated>2019-11-11T19:19:32Z</updated>
<entry>
<title>Merge tag 'u-boot-rockchip-20191110' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip</title>
<updated>2019-11-11T19:19:32Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-11-11T19:19:32Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=086e391bc46d3dda5c44053532bb51dc3827ee94'/>
<id>urn:sha1:086e391bc46d3dda5c44053532bb51dc3827ee94</id>
<content type='text'>
- Add support for rockchip pmic rk805,rk809, rk816, rk817
- Add rk3399 board Leez support
- Fix bug in rk3328 ram driver
- Adapt SPL to support ATF bl31 with entry at 0x40000
- Fix the u8 type comparision with '-1'.
- Fix checkpatch warning for multi blank line and review signature.
</content>
</entry>
<entry>
<title>clk: rockchip: rk3328: Configure CPU clock</title>
<updated>2019-11-10T12:40:20Z</updated>
<author>
<name>Simon South</name>
<email>simon@simonsouth.net</email>
</author>
<published>2019-10-10T19:28:36Z</published>
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<id>urn:sha1:2cbdb6e051c4a59335101f5ef2084c838b9b5399</id>
<content type='text'>
Add a call to rk3328_configure_cpu() during initialization to set the
CPU-clock frequency.

Signed-off-by: Simon South &lt;simon@simonsouth.net&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>clk: clk-ti-sci: Notify AVS driver upon setting clock rate</title>
<updated>2019-11-07T23:39:16Z</updated>
<author>
<name>Keerthy</name>
<email>j-keerthy@ti.com</email>
</author>
<published>2019-10-24T09:30:47Z</published>
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<id>urn:sha1:e0aa873bc7cd38d802cfdbe186fbbbafb9f6691e</id>
<content type='text'>
Notify AVS driver upon setting clock rate so that voltage
is changed accordingly.

Signed-off-by: Keerthy &lt;j-keerthy@ti.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-clk-23Oct2019' of https://gitlab.denx.de/u-boot/custodians/u-boot-clk</title>
<updated>2019-10-30T17:13:46Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-10-30T17:13:46Z</published>
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<id>urn:sha1:412326d1bc2d346d7b4faad6fa547eaf065681a2</id>
<content type='text'>
- Add I2C clocks for i.MX6Q CCF driver
- Fix check in clk_set_default_parents()
- Managed API to get clock from device tree
- Fixes for core clock code (including sandbox regression tests)
</content>
</entry>
<entry>
<title>Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mips</title>
<updated>2019-10-26T00:07:24Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-10-26T00:07:24Z</published>
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<id>urn:sha1:ffc379b42c85466e1dd4c8fee8268801f26d2ab8</id>
<content type='text'>
- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs
- bmips: various small fixes
- mtmips: add new drivers for clock, reset-controller and pinctrl
- mtmips: add support for high speed UART
- mtmips: update/enhance drivers for SPI and ethernet
- mtmips: add support for MMC
</content>
</entry>
<entry>
<title>clk: add clock driver for MediaTek MT76x8 platform</title>
<updated>2019-10-25T15:20:44Z</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2019-09-25T09:45:21Z</published>
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<id>urn:sha1:77ed3c42fee219fb50bca154b1ae36dbca8fc2e0</id>
<content type='text'>
This patch adds a clock driver for MediaTek MT7628/7688 SoC.
It provides clock gate control as well as getting clock frequency for
CPU/SYS/XTAL and some peripherals.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
</entry>
<entry>
<title>arm64: zynqmp: Switch to xlnx-zynqmp-clk header</title>
<updated>2019-10-24T11:37:02Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2019-10-14T13:42:03Z</published>
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<id>urn:sha1:039c740d662b1d7ee472bd0246aff3f770fbf1b0</id>
<content type='text'>
Use prepared header instead of hardcoded values.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>arm64: versal: Rename versal_pm_request to xilinx_pm_request</title>
<updated>2019-10-24T11:37:01Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2019-10-04T13:52:43Z</published>
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<id>urn:sha1:6596270ecb5d74d5f997da0daa728e06d1f47029</id>
<content type='text'>
Use generic name instead of Versal specific because this should be also
used on ZynqMP.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>arm64: versal: Clean pm_api_id usage</title>
<updated>2019-10-24T11:37:01Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2019-10-04T13:25:18Z</published>
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<id>urn:sha1:0f3604a2b3882bc0f6c66cfd5acbd074703a5814</id>
<content type='text'>
Copy enum values from platform code to firmware code. IDs are shared
between ZynqMP and Versal.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>test: clk: test clock self assignment</title>
<updated>2019-10-22T14:14:05Z</updated>
<author>
<name>Jean-Jacques Hiblot</name>
<email>jjhiblot@ti.com</email>
</author>
<published>2019-10-22T12:00:07Z</published>
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<id>urn:sha1:9a52be129c5b159269ac69a7ae0197eb02612f1d</id>
<content type='text'>
Make sure that the clock self-assignment works by having a clock of
clk-sbox be configured automatically when clk-sbox is probed.

Signed-off-by: Jean-Jacques Hiblot &lt;jjhiblot@ti.com&gt;
</content>
</entry>
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