This commit (82de42fa14682d408da935adfb0f935354c5008f) calls child's
ofdata_to_platdata() method before the parent is probed in dm core.
This has caused the driver no longer able to get the correct parent
clock's register base in the ofdata_to_platdata() method because the
parent clocks will only be probed after the child's ofdata_to_platdata().
To resolve this, the clock parent's register base will only be retrieved
by the child in probe() method instead of ofdata_to_platdata().

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>

During vidconsole probe, the device probe will try to
check whether the assigned clocks on that video console
node is initialized or not? and return an error if not.

But, unlike Linux U-Boot won't require to handle these
vopl assigned-clocks since core clocks are enough to
handle the video out to process.

So, mark them as empty in set_rate to satisfy clk_set_defaults
so-that probe happened properly.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>

The fdtdec_get_addr() does not take into account values set in #address-cells
and #size-cells , but assumes them to be 1 for 32bit systems and 2 for 64bit
systems. This is true for most DTs, however there are exceptions. Switch to
fdtdec_get_addr_size_auto_noparent(), which takes the #address/size-cells
values into consideration, otherwise the reset controller node register
offset is incorrectly parsed.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

If all branches of a switch statement have a return instruction, all
subsequent lines are unreachable.

Identified with cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

The clock driver makes EEMI call to get the name of invalid clk
when executing versal_get_clock_info() function. This results in
error messages.
Added check for validating clock before saving clock attribute and
calling versal_pm_clock_get_name() in versal_get_clock_info() function.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

- add DH Electronics DHCOM SoM and PDK2 board
- DT alignment with kernel v5.5-rc7 for stm32mp1 boards
- fix STM32 image format for big endian hosts in mkimage
- solve warnings in device tree and code for stm32mp1 boards
- remove fdt_high and initrd_high for stm32 and stih boards
- add support of STM32MP15x Rev.Z
- update stm32mp1 readme

Solve type issue in stm32mp1_lse_enable and stm32mp1_clktree.

This patch solves the warnings when compiling with W=1
on stm32mp1 board:

clk_stm32mp1.c: In function ‘stm32mp1_lse_enable’:
clk_stm32mp1.c:1238:15: warning: comparison of integer expressions
  of different signedness: ‘u32’ {aka ‘unsigned int’} and ‘int’
  [-Wsign-compare]
clk_stm32mp1.c:1239:13: warning: comparison of integer expressions
  of different signedness: ‘u32’ {aka ‘unsigned int’} and ‘int’
  [-Wsign-compare]

clk_stm32mp1.c: In function ‘stm32mp1_clktree’:
clk_stm32mp1.c:1814:17: warning: comparison of integer expressions
  of different signedness: ‘int’ and ‘unsigned int’
  [-Wsign-compare]

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>

HDMI PLL has its own xtal with 27 MHz output but we treat it the same
way as other PLLs with 33.33 MHz input.
Fix that.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Pll bypass has priority over enable/disable.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

sandbox conversion to SDL2
TPM TEE driver
Various minor sandbox video enhancements
New driver model core utility functions