u-boot.git/drivers/clk, branch v2020.07

rockchip: clk: rk3188: change APLL to safe 600MHz

2020-06-27T15:23:00+00:00

The commit 84a6a27ae3ff ("rockchip: rk3188: init CPU freq in clock
driver") changed ARM clock from 600MHz to 1600MHz. It made boot
unstable due to the fact that PMIC at the start generates insufficient
voltage for operation. See also: commit f4f57c58b589 ("rockchip:
rk3188: Setup the armclk in spl").

Fixes commit 84a6a27ae3ff ("rockchip: rk3188: init CPU freq in clock
driver").

Signed-off-by: Alexander Kochetkov 
Reviewed-by: Kever Yang

clk: sifive: fu540-prci: Release ethernet clock reset

2020-06-04T01:44:09+00:00

U-Boot ethernet works with FSBL flow where releasing ethernet clock
reset is part of FSBL itself but with the SPL, We need to release
ethernet clock reset explicitly for U-Boot proper. With this change
Release ethernet clock reset code in FSBL might not be needed or
unaffected.

Signed-off-by: Pragnesh Patel 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng

clk: sifive: fu540-prci: Add ddr clock initialization

2020-06-04T01:44:08+00:00

Release ddr clock reset once clock is initialized

Signed-off-by: Pragnesh Patel 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Reviewed-by: Jagan Teki 
Tested-by: Jagan Teki

clk: sifive: fu540-prci: Add clock enable and disable ops

2020-06-04T01:44:08+00:00

Added clock enable and disable functions in prci ops

Signed-off-by: Pragnesh Patel 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
Acked-by: Jagan Teki 
Tested-by: Jagan Teki

clk: rk3399: Enable/Disable TCPHY clocks

2020-05-29T10:08:49+00:00

Enable/Disable TCPHY clock for rk3399 platform.

Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang

clk: rk3399: Set empty for TCPHY assigned-clocks

2020-05-29T10:08:49+00:00

Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi
have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks
which are usually required for Linux and don't require to
handle them in U-Boot.

  assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
  assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;

So, mark them as empty in clock otherwise device probe on
those typec phy driver would fail.

Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang

clk: rk3399: Enable/Disable the USB2PHY clk

2020-05-29T10:08:49+00:00

Enable/Disable the USB2PHY clk for rk3399.

CLK is clear in enable and set in disable functionality.

Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang

clk: rk3399: Fix eMMC get_clk reg offset

2020-05-29T09:58:33+00:00

Actual eMMC get_clk register is clksel_con22 instead of
clksel_con21.

Fix it.

Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang

clk: rk3399: Enable/Disable the PCIEPHY clk

2020-05-22T12:53:20+00:00

Enable/Disable the PCIEPHY clk for rk3399.

CLK is clear in both enable and disable functionality.

Signed-off-by: Jagan Teki 
Tested-by: Suniel Mahesh  #roc-rk3399-pc
Reviewed-by: Kever Yang

clk: rk3399: Add enable/disable clks

2020-05-22T12:53:20+00:00

Yes, most of the high speed peripheral clocks
in rk3399 enabled by default.

But it would be better to handle them via clk
enable/disable API for handling proper reset
conditions like 'usb reset' over command line.

So, enable USB, GMAC clock via enable/disable ops.

Signed-off-by: Jagan Teki 
Tested-by: Suniel Mahesh  # roc-rk3399-pc
Tested-by: Suniel Mahesh  #roc-rk3399-pc
Reviewed-by: Kever Yang