u-boot.git/drivers/clk, branch v2020.07-rc2

Merge tag 'u-boot-imx-20200502' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

2020-05-04T13:29:42Z

i.MX for 2020.07 ---------------- - imxrt: fix LCD clock, fix doc - new board: Coral Dev - imx8: enable Cache in SPL. SNVS, update SCFW API - imx8MM: fix reset, 8MQ quand and QuadLite, CPU speed grading - MX6ULL : is_imx6ull to include i.MX6ULZ - Net: add config to enable TXC delay Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/682033914

Merge tag 'u-boot-rockchip-20200501' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip

2020-05-04T11:28:14Z

- dts clean up to use -u-boot for px30, rk3399 boards - dts sycn from upstream kernel for rk3328, rk3399 - add rockchip rng driver - new board support: rk3328-roc-cc, rk3399-roc-pc,Nanopi M4 2GB

clk: imx: clk-imxrt1050: fix lcdif clock gate

2020-05-01T17:03:25Z

LCDIF clock gate was wrong so set it according to RM. Signed-off-by: Giulio Benetti Reviewed-by: Anatolij Gustschin Reviewed-by: Fabio Estevam

clk: rk3399: Set empty for HCLK_SD assigned-clocks

2020-05-01T10:32:56Z

Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi have HCLK_SD assigned-clocks which are usually required for Linux and don't require to handle them in U-Boot. assigned-clocks = <&cru HCLK_SD>; So, mark them as empty in clock otherwise device probe on those SD controllers would fail. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang

Merge tag 'xilinx-for-v2020.07-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

2020-04-30T15:34:01Z

Xilinx changes for v2020.07-rc2 mmc: - Fix dt property handling via generic function clk: - Fix versal watchdog clock setting nand: - Fix zynq nand command comparison xilinx: - Enable ubifs - Sync board_late_init configurations with initrd_high setup - Make custom distro boot more verbose zynq: - Kconfig alignments - Fix nand cse configuration zynqmp: - Fix zcu104 low level qspi configuration - Small DT updates Signed-off-by: Tom Rini

Merge tag 'u-boot-amlogic-20200428' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

2020-04-28T14:09:16Z

- fix sd-emmc controller A init on G12A/G12B/SM1 SoCs - add GXBB USB PHY driver - enable access to SPI NOR Flash on VIM2 and VIM3/VIM3L boards - fix USB PHYs Power-Up on on VIM3/VIM3L boards

clk: meson: g12a: add missing SD_EMMC_A controller gates

2020-04-28T08:23:10Z

Add missing SD_EMMC_A controller gates needed for probe of the A controller, otherwise leading to a freeze of the SoC after b3d69aa596. Fixes: b3d69aa596 ("clk: meson: reset mmc clock on probe") Signed-off-by: Neil Armstrong

clk: versal: Fix watchdog clock issue

2020-04-27T11:57:17Z

Enable mux based clocks to populate LPD_LSBUS clock to xilinx_wwdt driver. Skip reading clock rate for the mux based clocks with parent clock id is zero. Signed-off-by: T Karthik Reddy Signed-off-by: Ashok Reddy Soma

ARC: HSDK: CGU: add support for timer clock

2020-04-27T08:20:25Z

Add support for additional timer clock which belongs to tunnel domain. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

clk: actions: Add common clock driver

2020-04-24T20:40:09Z

This patch converts S900 clock driver to something common that can be used for other SoCs, for instance S700(few of clk registers are same). Reviewed-by: Andre Przywara Signed-off-by: Amit Singh Tomar