u-boot.git/drivers/clk, branch v2020.07-rc5

clk: sifive: fu540-prci: Release ethernet clock reset

2020-06-04T01:44:09Z

U-Boot ethernet works with FSBL flow where releasing ethernet clock reset is part of FSBL itself but with the SPL, We need to release ethernet clock reset explicitly for U-Boot proper. With this change Release ethernet clock reset code in FSBL might not be needed or unaffected. Signed-off-by: Pragnesh Patel Reviewed-by: Bin Meng Tested-by: Bin Meng

clk: sifive: fu540-prci: Add ddr clock initialization

2020-06-04T01:44:08Z

Release ddr clock reset once clock is initialized Signed-off-by: Pragnesh Patel Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Jagan Teki Tested-by: Jagan Teki

clk: sifive: fu540-prci: Add clock enable and disable ops

2020-06-04T01:44:08Z

Added clock enable and disable functions in prci ops Signed-off-by: Pragnesh Patel Reviewed-by: Bin Meng Tested-by: Bin Meng Acked-by: Jagan Teki Tested-by: Jagan Teki

clk: rk3399: Enable/Disable TCPHY clocks

2020-05-29T10:08:49Z

Enable/Disable TCPHY clock for rk3399 platform. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang

clk: rk3399: Set empty for TCPHY assigned-clocks

2020-05-29T10:08:49Z

Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks which are usually required for Linux and don't require to handle them in U-Boot. assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; So, mark them as empty in clock otherwise device probe on those typec phy driver would fail. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang

clk: rk3399: Enable/Disable the USB2PHY clk

2020-05-29T10:08:49Z

Enable/Disable the USB2PHY clk for rk3399. CLK is clear in enable and set in disable functionality. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang

clk: rk3399: Fix eMMC get_clk reg offset

2020-05-29T09:58:33Z

Actual eMMC get_clk register is clksel_con22 instead of clksel_con21. Fix it. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang

clk: rk3399: Enable/Disable the PCIEPHY clk

2020-05-22T12:53:20Z

Enable/Disable the PCIEPHY clk for rk3399. CLK is clear in both enable and disable functionality. Signed-off-by: Jagan Teki Tested-by: Suniel Mahesh #roc-rk3399-pc Reviewed-by: Kever Yang

clk: rk3399: Add enable/disable clks

2020-05-22T12:53:20Z

Yes, most of the high speed peripheral clocks in rk3399 enabled by default. But it would be better to handle them via clk enable/disable API for handling proper reset conditions like 'usb reset' over command line. So, enable USB, GMAC clock via enable/disable ops. Signed-off-by: Jagan Teki Tested-by: Suniel Mahesh # roc-rk3399-pc Tested-by: Suniel Mahesh #roc-rk3399-pc Reviewed-by: Kever Yang

common: Drop linux/bitops.h from common header

2020-05-19T01:19:23Z

Move this uncommon header out of the common header. Signed-off-by: Simon Glass