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<title>u-boot.git/drivers/clk, branch v2021.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>Merge tag 'u-boot-atmel-fixes-2021.01-b' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel</title>
<updated>2020-12-11T20:55:17+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2020-12-11T20:55:17+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5a1a8a63be8f7262a300eddafb18020926b12fb6'/>
<id>5a1a8a63be8f7262a300eddafb18020926b12fb6</id>
<content type='text'>
Second set of u-boot-atmel fixes for 2021.01 cycle

This set includes very important fixes for: MMC booting on several
boards, drive strength on sam9x60ek mmc lines, compile issues for
timer.c old driver, removal of unwanted access to sam9x60 bit for
oscillator bypass mode, and eeproms read on sama5d2_icp.
</content>
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<pre>
Second set of u-boot-atmel fixes for 2021.01 cycle

This set includes very important fixes for: MMC booting on several
boards, drive strength on sam9x60ek mmc lines, compile issues for
timer.c old driver, removal of unwanted access to sam9x60 bit for
oscillator bypass mode, and eeproms read on sama5d2_icp.
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-stm32-20201209' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm</title>
<updated>2020-12-09T16:36:41+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2020-12-09T16:36:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2a42de6df1ac75bd85bdb1dd8580f01895c915cd'/>
<id>2a42de6df1ac75bd85bdb1dd8580f01895c915cd</id>
<content type='text'>
- Manage CONFIG_ENV_EXT4_DEVICE_AND_PART in stm32mp1 board
- Update ARM STI and ARM STM STM32MP Arch maintainers emails
- Enable internal pull-ups for SDMMC1 on DHCOM SoM
</content>
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<pre>
- Manage CONFIG_ENV_EXT4_DEVICE_AND_PART in stm32mp1 board
- Update ARM STI and ARM STM STM32MP Arch maintainers emails
- Enable internal pull-ups for SDMMC1 on DHCOM SoM
</pre>
</div>
</content>
</entry>
<entry>
<title>treewide: Update email address Patrick Delaunay and Patrice Chotard</title>
<updated>2020-12-09T09:57:50+00:00</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@foss.st.com</email>
</author>
<published>2020-12-02T17:47:30+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0f8106f8e0c03839b371eaee1d7459b810d569ec'/>
<id>0f8106f8e0c03839b371eaee1d7459b810d569ec</id>
<content type='text'>
Update Patrick and my email address with the one dedicated to
upstream activities.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
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<pre>
Update Patrick and my email address with the one dedicated to
upstream activities.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: at91: sam9x60: remove the parsing of atmel, main-osc-bypass</title>
<updated>2020-12-07T07:36:45+00:00</updated>
<author>
<name>Claudiu Beznea</name>
<email>claudiu.beznea@microchip.com</email>
</author>
<published>2020-12-02T11:39:33+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8454cf0d236639f36f465b5b5cf4ef8b572698b6'/>
<id>8454cf0d236639f36f465b5b5cf4ef8b572698b6</id>
<content type='text'>
Remove the parsing of atmel,main-osc-bypass DT property as the SAM9X60
have no support for crystal oscillator bypass. Setting this bit might
affect the device functionality.

Fixes: a64862284f65 ("clk: at91: sam9x60: add support compatible with CCF")
Signed-off-by: Claudiu Beznea &lt;claudiu.beznea@microchip.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Remove the parsing of atmel,main-osc-bypass DT property as the SAM9X60
have no support for crystal oscillator bypass. Setting this bit might
affect the device functionality.

Fixes: a64862284f65 ("clk: at91: sam9x60: add support compatible with CCF")
Signed-off-by: Claudiu Beznea &lt;claudiu.beznea@microchip.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>imx: clk: added IPG Clock for I2C on imx8qm</title>
<updated>2020-12-06T14:07:51+00:00</updated>
<author>
<name>Oliver Graute</name>
<email>oliver.graute@kococonnector.com</email>
</author>
<published>2020-11-12T10:51:04+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=61eb1fe56849c1418f35c5a9579047ab113e914f'/>
<id>61eb1fe56849c1418f35c5a9579047ab113e914f</id>
<content type='text'>
This patch fixes this clk issue on I2C on imx8qm

 =&gt; i2c bus
 Bus 3:  i2c@5a830000
 =&gt; i2c dev 3
 Setting bus to 3
 Failed to enable ipg clk
 Failure changing bus number (-524)

Signed-off-by: Oliver Graute &lt;oliver.graute@kococonnector.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: uboot-imx &lt;uboot-imx@nxp.com&gt;
Reviewed-by: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
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<pre>
This patch fixes this clk issue on I2C on imx8qm

 =&gt; i2c bus
 Bus 3:  i2c@5a830000
 =&gt; i2c dev 3
 Setting bus to 3
 Failed to enable ipg clk
 Failure changing bus number (-524)

Signed-off-by: Oliver Graute &lt;oliver.graute@kococonnector.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: uboot-imx &lt;uboot-imx@nxp.com&gt;
Reviewed-by: Stefano Babic &lt;sbabic@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: sunxi: add compatible string for V3</title>
<updated>2020-11-17T00:42:21+00:00</updated>
<author>
<name>Icenowy Zheng</name>
<email>icenowy@aosc.io</email>
</author>
<published>2020-10-26T14:18:02+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6ffdc43cc5e6070edf91bac653cc8a0449dbe545'/>
<id>6ffdc43cc5e6070edf91bac653cc8a0449dbe545</id>
<content type='text'>
A new compatible string is introduced for V3 CCU, because it has a few
extra features available.

Add the compatible string to the clock driver. As the extra features are
not touched, just share the description struct now.

Signed-off-by: Icenowy Zheng &lt;icenowy@aosc.io&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
A new compatible string is introduced for V3 CCU, because it has a few
extra features available.

Add the compatible string to the clock driver. As the extra features are
not touched, just share the description struct now.

Signed-off-by: Icenowy Zheng &lt;icenowy@aosc.io&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: rk3399: Init clocks in U-Boot proper if SPL was not run</title>
<updated>2020-11-13T10:15:08+00:00</updated>
<author>
<name>Alper Nebi Yasak</name>
<email>alpernebiyasak@gmail.com</email>
</author>
<published>2020-10-27T21:15:10+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=eb89025013a6d4b1d9cf307e5a2a087196ee9f02'/>
<id>eb89025013a6d4b1d9cf307e5a2a087196ee9f02</id>
<content type='text'>
It's possible to chainload U-Boot proper from the vendor firmware in
rk3399 chromebooks, but the way the vendor firmware sets up clocks is
somehow different than what U-Boot expects. This causes the display to
stay devoid of content even though vidconsole claims to work (with
patches in process of being upstreamed).

This is meant to be a rk3399 version of commit d3cb46aa8c41 ("rockchip:
Init clocks again when chain-loading") which can detect the discrepancy,
but this patch instead checks whether SPL (and therefore the clock init)
was run via the handoff functionality and runs the init if it was not.

Signed-off-by: Alper Nebi Yasak &lt;alpernebiyasak@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Kever Yang&lt;kever.yang@rock-chips.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
It's possible to chainload U-Boot proper from the vendor firmware in
rk3399 chromebooks, but the way the vendor firmware sets up clocks is
somehow different than what U-Boot expects. This causes the display to
stay devoid of content even though vidconsole claims to work (with
patches in process of being upstreamed).

This is meant to be a rk3399 version of commit d3cb46aa8c41 ("rockchip:
Init clocks again when chain-loading") which can detect the discrepancy,
but this patch instead checks whether SPL (and therefore the clock init)
was run via the handoff functionality and runs the init if it was not.

Signed-off-by: Alper Nebi Yasak &lt;alpernebiyasak@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Kever Yang&lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-rockchip-20201031' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip</title>
<updated>2020-10-31T03:13:13+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2020-10-31T02:55:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2c31d7e746766f47a007f39c030706e493a9cc77'/>
<id>2c31d7e746766f47a007f39c030706e493a9cc77</id>
<content type='text'>
- New PX30 board: Engicam PX30.Core;
- Fix USB HID support for rock960;
- Remove host endianness dependency for rockchip mkimage;
- dts update for rk3288-tinker;
- Enable console MUX for some ROCKPi boards;
- Add config-based ddr selection for px30;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
- New PX30 board: Engicam PX30.Core;
- Fix USB HID support for rock960;
- Remove host endianness dependency for rockchip mkimage;
- dts update for rk3288-tinker;
- Enable console MUX for some ROCKPi boards;
- Add config-based ddr selection for px30;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: rockchip: rk3399: implement getting wdt/alive clocks</title>
<updated>2020-10-30T10:05:45+00:00</updated>
<author>
<name>Jack Mitchell</name>
<email>ml@embed.me.uk</email>
</author>
<published>2020-09-17T09:42:06+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=da0be4e176dcd86fb4d18a31b5be9822d5463f83'/>
<id>da0be4e176dcd86fb4d18a31b5be9822d5463f83</id>
<content type='text'>
In order to correctly calculate the designware watchdog
timeouts, the watchdog clock is required. Implement required
clocks to facilitate this.

Signed-off-by: Jack Mitchell &lt;ml@embed.me.uk&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In order to correctly calculate the designware watchdog
timeouts, the watchdog clock is required. Implement required
clocks to facilitate this.

Signed-off-by: Jack Mitchell &lt;ml@embed.me.uk&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: Use driver_info index instead of pointer</title>
<updated>2020-10-29T20:42:18+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-10-03T17:31:40+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8a38abfc43f94a92b63e428738714111710bda53'/>
<id>8a38abfc43f94a92b63e428738714111710bda53</id>
<content type='text'>
At present we use a 'node' pointer in the of-platadata phandle_n_arg
structs. This is a pointer to the struct driver_info for a particular
device, and we can use it to obtain the struct udevice pointer itself.

Since we don't know the struct udevice pointer until it is allocated in
memory, we have to fix up the phandle_n_arg.node at runtime. This is
annoying since it requires that SPL's data is writable and adds a small
amount of extra (generated) code in the dm_populate_phandle_data()
function.

Now that we can find a driver_info by its index, it is easier to put the
index in the phandle_n_arg structures.

Update dtoc to do this, add a new device_get_by_driver_info_idx() to look
up a device by drive_info index and update the tests to match.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
At present we use a 'node' pointer in the of-platadata phandle_n_arg
structs. This is a pointer to the struct driver_info for a particular
device, and we can use it to obtain the struct udevice pointer itself.

Since we don't know the struct udevice pointer until it is allocated in
memory, we have to fix up the phandle_n_arg.node at runtime. This is
annoying since it requires that SPL's data is writable and adds a small
amount of extra (generated) code in the dm_populate_phandle_data()
function.

Now that we can find a driver_info by its index, it is easier to put the
index in the phandle_n_arg structures.

Update dtoc to do this, add a new device_get_by_driver_info_idx() to look
up a device by drive_info index and update the tests to match.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
