u-boot.git/drivers/clk, branch v2021.10

clk: ti: k3: Update driver to account for divider flags

2021-09-17T18:47:03Z

The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna Signed-off-by: Dave Gerlach

clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-write

2021-09-17T18:47:03Z

There are three different divider values in the DIV_CTRL register controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate function writes the entire register when programming plld, even though plld only resides in the lower 6 bits. Change the plld programming to read-modify-write to only affect the relevant bits for plld and to preserve the other two divider values present in the upper 16 bits, otherwise they will always get set to zero when programming plld. Fixes: 0aa2930ca192 ("clk: add support for TI K3 SoC PLL") Signed-off-by: Dave Gerlach

drivers: clk: Add memory clock driver for Intel N5X device

2021-08-25T04:55:13Z

Add memory clock manager driver for N5X. Provides memory clock initialization and enable functions. Signed-off-by: Siew Chin Lim

drivers: clk: Add clock driver for Intel N5X device

2021-08-25T04:51:53Z

Add clock manager driver for N5X. Provides clock initialization and get_rate functions. Signed-off-by: Siew Chin Lim

clk: clk_versaclock: Add support for versaclock driver

2021-08-21T22:23:02Z

The driver is based on the Versaclock driver from the Linux code, but due differences in the clock API between them, some pieces had to be changed. This driver creates a mux, pfd, pll, and a series of fod ouputs. Rate Usecnt Name ------------------------------------------ 25000000 0 `-- x304-clock 25000000 0 `-- clock-controller@6a.mux 25000000 0 |-- clock-controller@6a.pfd 2800000000 0 | `-- clock-controller@6a.pll 33333333 0 | |-- clock-controller@6a.fod0 33333333 0 | | `-- clock-controller@6a.out1 33333333 0 | |-- clock-controller@6a.fod1 33333333 0 | | `-- clock-controller@6a.out2 50000000 0 | |-- clock-controller@6a.fod2 50000000 0 | | `-- clock-controller@6a.out3 125000000 0 | `-- clock-controller@6a.fod3 125000000 0 | `-- clock-controller@6a.out4 25000000 0 `-- clock-controller@6a.out0_sel_i2cb A translation function is added so the references to <&versaclock X> get routed to the corresponding clock-controller@6a.outX. Signed-off-by: Adam Ford Reviewed-by: Sean Anderson

clk: stm32mp1: add support of BSEC clock

2021-08-16T07:33:43Z

Add the support of the BSEC clock used by the STM32MP misc driver since the commit 622c956cada0 ("stm32mp: bsec: manage clock when present in device tree") even if this clock is not yet defined in kernel device tree stm32mp151.dtsi. This patch avoids issue for basic boot when this secure clock are not provided by secure world with SCMI. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard

rockchip: px30: Support configure SFC

2021-08-12T01:34:11Z

Make px30 SFC clock configurable Signed-off-by: Jon Lin Reviewed-by: Jagan Teki Reviewed-by: Kever Yang

clk: stm32mp1: add support of missing SPI clocks

2021-07-27T07:47:40Z

Add the missing SPI clock even if these instances are not available on STMicroelectronics boards: SPI2_K, SPI3_K, SPI4_K, SPI6_K. With this patch, the SPI2 / SPI3 / SPI4 / SPI6 instances can be used on customer design without the clock driver error: stm32mp1_clk_get_id: clk id 131 not found Reviewed-by: Patrice Chotard Signed-off-by: Patrick Delaunay

clk: zynqmp: Add support for enabling clock on lpd_lsbus

2021-07-26T07:18:45Z

lpd_lsbus is clock which is used by many IPs like dmas, gems, gpio, sdhcis, spis, ttcs, uarts, watchdog that's why make sense to also enable access to change this clock. For this clock you already get the rate. Signed-off-by: Michal Simek

Merge tag 'u-boot-imx-20210717' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

2021-07-17T14:52:21Z

i.MX ---- - mx7ulp : fix WDOG - imx8 : Phytec - USB3 support for i.MX8 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277