u-boot.git/drivers/clk, branch v2022.01-rc2

stm32mp15: replace CONFIG_TFABOOT when it is possible

2021-11-10T16:07:31Z

In some part of STM32MP15 support the CONFIG_TFABOOT can be replaced by other config: CONFIG_ARMV7_PSCI and CONFIG_ARM_SMCCC. This patch also simplifies the code in cpu.c, stm32mp1_ram.c and clk_stml32mp1.c as execution of U-Boot in sysram (boot without SPL and without TFA) is not supported: the associated initialization code is present only in SPL. This cleanup patch is a preliminary step to support SPL load of OP-TEE in secure world, with SPL in secure world and U-Boot in no-secure world. Reported-by: Alexandru Gagniuc Signed-off-by: Patrick Delaunay

clk: sunxi: Extend DM_RESET selection to SPL

2021-10-25T13:54:06Z

The sunxi clock driver exposes a reset controller, so it selects the reset controller framework. Ensure that dependency is also satisfied when building the driver for the SPL. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara

clk: sifive: Fix -Wint-to-pointer-cast warning

2021-10-20T02:59:09Z

dev_read_addr() returns a value of type fdt_addr_t which is a 64-bit address and pd->va is a pointer. In a 32-bit build, this causes the following warning seen when building sifive-prci.c: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Change to use dev_read_addr_ptr(). Signed-off-by: Bin Meng Reviewed-by: Leo Yu-Chi Liang

clk: fixed_rate: add dummy disable() function

2021-10-19T15:25:25Z

commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function") implemented .enable, so fixed rate clocks can be used where drivers might call clk_enable(). Implement the .disable op for the same reason; some drivers, e.g. USB PHYs, may attempt to disable clocks at runtime. Signed-off-by: Samuel Holland

clk: rockchip: rk3568: update clks

2021-10-15T12:57:31Z

fix up ppll init freq. support tclk_emmc. add freq (26M) for mmc device. fix up the sfc clk rate unit error. Change in V2: remove change id. Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang

rockchip: px30: add support for setting cpll clock

2021-10-15T12:56:09Z

Starting with commit 92f1e9a4b31c ("clk: Detect failure to set defaults") the clk driver for the PX30 for the Odroid Go Advance would no longer probe correctly, because setting the cpll and gpu clocks are not supported with the clk_px30 U-Boot driver. This adds support for setting the cpll clock to the clk_px30 driver. Another patch will update the U-Boot specific device-tree to remove the GPU clock which is not used by U-Boot. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang

Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi

2021-10-12T15:45:00Z

The bulk of it is Samuel's DM_I2C rework, which removes the nasty I2C deprecation warnings for most 32-bit boards. It also includes some smaller refactorings that pave the way for more changes, mostly driven by needing to support the Allwinner RISC-V SoC later on. Board wise we gain support for the FriendlyARM NanoPi R1S H5 router board and official Pinetab support. Build-tested for all 160 sunxi boards, and boot tested on a A64, A20, H3, H6, and H616 board. USB, SD card, eMMC, and Ethernet all work there (where applicable).

clk: ti: add am33xx/am43xx spread spectrum clock support

2021-10-11T18:27:32Z

The patch enables spread spectrum clocking (SSC) for MPU and LCD PLLs. As reported by the TI spruh73x/spruhl7x RM, SSC is only supported for the DISP/LCD and MPU PLLs on am33xx/am43xx. SSC is not supported for DDR, PER, and CORE PLLs. Calculating the required values and setting the registers accordingly was taken from the set_mpu_spreadspectrum routine contained in the arch/arm/mach-omap2/am33xx/clock_am33xx.c file of the u-boot project. In locked condition, DPLL output clock = CLKINP *[M/N]. In case of SSC enabled, the reference manual explains that there is a restriction of range of M values. Since the clk_ti_am3_dpll_round_rate() attempts to select the minimum possible N, the value of M obtained is not guaranteed to be within the range required. With the new "ti,min-div" parameter it is possible to increase N and consequently M to satisfy the constraint imposed by SSC. Link: https://lore.kernel.org/r/20210606202253.31649-6-dariobin@libero.it Signed-off-by: Dario Binacchi

clk: sunxi: Add drivers for A31 and H6 PRCM CCUs

2021-10-11T09:46:44Z

Add a driver so the clocks/resets for these peripherals (especially I2C, RSB, and UART) can be enabled using the normal uclass methods. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara

clk: sunxi: Add support for I2C gates/resets

2021-10-11T09:46:44Z

Currently, the I2C clocks are configured in the sunxi board code. Add the I2C clocks to the DM clock driver so they can be enabled from the DM I2C driver using the normal uclass methods. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara