<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/clk, branch v2022.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/clk?h=v2022.07</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/clk?h=v2022.07'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2022-07-01T07:00:39Z</updated>
<entry>
<title>drivers: clk: Update license for Intel N5X device</title>
<updated>2022-07-01T07:00:39Z</updated>
<author>
<name>Teik Heng Chong</name>
<email>teik.heng.chong@intel.com</email>
</author>
<published>2022-06-29T05:51:50Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ef5ba2cef4a08b68caaa9215fcac142d3025bbf7'/>
<id>urn:sha1:ef5ba2cef4a08b68caaa9215fcac142d3025bbf7</id>
<content type='text'>
All the source code of clk-mem-n5x.c and clk-n5x.c are from Intel,
update the license to use both GPL2.0 and BSD-3 Clause because this
copy of code may used for open source and internal project.

Signed-off-by: Teik Heng Chong &lt;teik.heng.chong@intel.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</content>
</entry>
<entry>
<title>clk: sunxi: Add additional RTC compatible strings</title>
<updated>2022-06-26T10:22:53Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2022-05-01T03:38:36Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=33112ae0214ed6b260fc982329d02253eab3e35d'/>
<id>urn:sha1:33112ae0214ed6b260fc982329d02253eab3e35d</id>
<content type='text'>
Compatible strings for some new RTC hardware variants were added to
the binding. Add them to the driver in preparation for supporting
those new SoCs.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>clk: imx8mp: use usb_core_ref for usb_root_clk</title>
<updated>2022-06-14T19:25:26Z</updated>
<author>
<name>Andrey Zhizhikin</name>
<email>andrey.zhizhikin@leica-geosystems.com</email>
</author>
<published>2022-06-03T15:15:22Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=65d5931d02d47eacdb26b879a252064bf728ae12'/>
<id>urn:sha1:65d5931d02d47eacdb26b879a252064bf728ae12</id>
<content type='text'>
Upstream commit 7a2c3be95a50 ("clk: imx8mp: Fill in DWC3 USB, USB PHY,
HSIOMIX clock") added usb_core_ref for USB Controller but never set it
to be used as a clock source, using rather "osc_32k" instead.

This produces following boot log message:
"clk_register: failed to get osc_32k device (parent of usb_root_clk)"

Fix the USB controller clock source by using usb_core_ref instead of
osc_32k.

Fixes: 7a2c3be95a50 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock")
Signed-off-by: Andrey Zhizhikin &lt;andrey.zhizhikin@leica-geosystems.com&gt;
Cc: Fabio Estevam &lt;festevam@denx.de&gt;
Cc: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Reviewed-by: Fabio Estevam &lt;festevam@denx.de&gt;
</content>
</entry>
<entry>
<title>clk: imx8mp: fix root clock names for ecspi</title>
<updated>2022-06-14T19:25:26Z</updated>
<author>
<name>Andrey Zhizhikin</name>
<email>andrey.zhizhikin@leica-geosystems.com</email>
</author>
<published>2022-06-03T15:15:21Z</published>
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<id>urn:sha1:698c0411cfabcd245027400961d184d0e072a22c</id>
<content type='text'>
Root clock name contained underscore, which does not match to the actual
clock name.

Correct the name to match what is present in the FDT.

Fixes: 87f958810fcb ("clk: imx8mp: Add ECSPI clocks")
Signed-off-by: Andrey Zhizhikin &lt;andrey.zhizhikin@leica-geosystems.com&gt;
Cc: Fabio Estevam &lt;festevam@denx.de&gt;
Cc: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: uboot-imx &lt;uboot-imx@nxp.com&gt;
Reviewed-by: Fabio Estevam &lt;festevam@denx.de&gt;
</content>
</entry>
<entry>
<title>clk: sunxi: add and use dummy gate clocks</title>
<updated>2022-05-24T00:16:15Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2022-05-05T00:25:43Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d6cb09d89d52d087881695c1f4e5e1ff26328267'/>
<id>urn:sha1:d6cb09d89d52d087881695c1f4e5e1ff26328267</id>
<content type='text'>
Some devices enumerate various clocks in their DT, and many drivers
just blanketly try to enable all of them. This creates problems
since we only model a few gate clocks, and the clock driver outputs
a warning when a clock is not described:
=========
sunxi_set_gate: (CLK#3) unhandled
=========

Some clocks don't have an enable bit, or are already enabled in a
different way, so we might want to just ignore them.

Add a CCU_CLK_F_DUMMY_GATE flag that indicates that case, and define
a GATE_DUMMY macro that can be used in the clock description array.
Define a few clocks, used by some pinctrl devices, that way to suppress
the runtime warnings.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Reviewed-by: Samuel Holland &lt;samuel@sholland.org&gt;
</content>
</entry>
<entry>
<title>clk: sunxi: add PIO bus gate clocks</title>
<updated>2022-05-24T00:15:09Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2022-05-04T21:10:28Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=444ab3569bae32daed9c05fb10f87d907cc180ff'/>
<id>urn:sha1:444ab3569bae32daed9c05fb10f87d907cc180ff</id>
<content type='text'>
The introduction of the DM pinctrl driver made its probe function enable
all clocks enumerated in the DT. This includes the "CLK_BUS_PIO" (and
variations) gate clock. Also CLK_PLL_PERIPH0 is used by the R_CCU device.
So far we didn't describe those clocks in our clock driver.
As we enable them already in the SPL, the devices happen to work, but
the clock driver still complains about not finding those clocks:
=========
sunxi_set_gate: (CLK#58) unhandled
=========

Add the one-liners that are needed to announce the gate bit for those
clocks, to silence that message on the console.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Reviewed-by: Samuel Holland &lt;samuel@sholland.org&gt;
</content>
</entry>
<entry>
<title>clk: sunxi: h6_r: Correct the driver name</title>
<updated>2022-05-24T00:15:01Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2022-04-23T21:07:16Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=596247e54b6243c53921a936fe3ce5ef031a702d'/>
<id>urn:sha1:596247e54b6243c53921a936fe3ce5ef031a702d</id>
<content type='text'>
H6 is from the sun50i family, not sun6i.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>clk: sunxi: implement clock driver for suniv f1c100s</title>
<updated>2022-05-22T23:37:51Z</updated>
<author>
<name>George Hilliard</name>
<email>thirtythreeforty@gmail.com</email>
</author>
<published>2021-07-25T23:16:23Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=89dd650f20ffc18372df1524ad0afbb93ce5a884'/>
<id>urn:sha1:89dd650f20ffc18372df1524ad0afbb93ce5a884</id>
<content type='text'>
The f1c100s has a clock tree similar to those of other sunxi parts.
Add support for it.

Signed-off-by: George Hilliard &lt;thirtythreeforty@gmail.com&gt;
Signed-off-by: Yifan Gu &lt;me@yifangu.com&gt;
Acked-by: Sean Anderson &lt;seanga2@gmail.com&gt;
[Andre: add PIO and I2C]
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>clk: stm32mp1: Add missing newline</title>
<updated>2022-05-10T11:56:11Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2022-04-22T10:40:39Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=05a3a028c127c7ca515b90a916cf3ac8c0264a61'/>
<id>urn:sha1:05a3a028c127c7ca515b90a916cf3ac8c0264a61</id>
<content type='text'>
Add missing newline to this debug message, no functional change.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
Cc: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
Signed-off-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
</content>
</entry>
<entry>
<title>clk: scmi: fix scmi_clk_get_attibute()</title>
<updated>2022-05-05T23:37:11Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>heinrich.schuchardt@canonical.com</email>
</author>
<published>2022-04-26T21:26:31Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d6577668196a130787291682ff9202721396ec1b'/>
<id>urn:sha1:d6577668196a130787291682ff9202721396ec1b</id>
<content type='text'>
Local variable out.name lives on the stack and therefore cannot
be returned directly. Move the strdup() call into the function.
(Coverity 352460)

Fixes: 7c33f78983c3 ("clk: scmi: register scmi clocks with CCF")
Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
Reviewed-by: Sean Anderson &lt;seanga2@gmail.com&gt;
</content>
</entry>
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