u-boot.git/drivers/clk, branch v2023.01

rockchip: rk3128-cru: sync the clock dt-binding header from Linux

2022-12-19T02:56:12+00:00

In order to update the DT for rk3128
sync the clock dt-binding header.
This is the state as of v6.0 in Linux.

Signed-off-by: Johan Jonker 
Reviewed-by: Kever Yang

clk: stm32mp13: introduce STM32MP13 RCC driver

2022-12-07T15:49:35+00:00

STM32MP13 RCC driver uses Common Clock Framework and also a
'clk-stm32-core' API. Then STM32MPx RCC driver will contain only data
configuration (gates, mux, dividers and the way to check security)
or some specific clocks.
This API will be used by all new other generations of ST Socs.

Signed-off-by: Gabriel Fernandez 
Reviewed-by: Patrick Delaunay 
Reviewed-by: Sean Anderson 
Tested-by: Patrick Delaunay 
Reviewed-by: Patrice Chotard

clk: microchip: mpfs: fix criticality of peripheral clocks

2022-11-15T07:37:17+00:00

Sync the critical clocks in the U-Boot driver with those marked as
critical in Linux. The Linux driver has an explanation of why each clock
is considered to be critical, so import that too.

Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley 
Reviewed-by: Leo Yu-Chi Liang 
Reviewed-by: Padmarao Begari

clk: microchip: mpfs: fix periph clk parentage

2022-11-15T07:37:17+00:00

Not all "periph" clocks are children of the AHB clock, some have the AXI
clock as their parent & the mtimer clock is derived from the external
reference clock directly. Stop assuming the AHB clock to be the parent
of all "periph" clocks and define their correct parents instead.

Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley 
Reviewed-by: Leo Yu-Chi Liang 
Reviewed-by: Padmarao Begari 
Tested-by: Padmarao Begari

clk: microchip: mpfs: fix reference clock handling

2022-11-15T07:37:17+00:00

The original devicetrees for PolarFire SoC messed up & defined the
msspll's output as a fixed-frequency, 600 MHz clock & used that as the
input for the clock controller node. The msspll is not a fixed
frequency clock and later devicetrees handled this properly. Check the
devicetree & if it is one of the fixed ones, register the msspll.
Otherwise, skip registering it & pass the reference clock directly to
the cfg clock registration function so that existing devicetrees are
not broken by this change.

As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for
it, based on the one in Linux.

Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley 
Reviewed-by: Leo Yu-Chi Liang 
Reviewed-by: Padmarao Begari 
Tested-by: Padmarao Begari

clk: microchip: mpfs: convert parent rate acquistion to get_get_rate()

2022-11-15T07:37:17+00:00

Currently the clock driver for PolarFire SoC takes a very naive approach
to the relationship between clocks. It reads the dt to get an input
clock, assumes that that is fixed frequency, reads the "clock-frequency"
property & uses that to set up both the "cfg" and "periph" clocks.

Simplifying for the sake of incremental fixes, the "correct" parentage for
the clocks currently supported in U-Boot is that the "cfg" clocks should
be children of the fixed frequency clock in the dt. The AHB clock is one
of these "cfg" clocks and is the parent of the "periph" clocks.

Instead of passing the clock rate of the fixed-frequency clock to the
"cfg" and "periph" registration functions and the name of the parents,
pass their actual parents & use clk_get_rate() to determine their parents
rates.

The "periph" clocks are purely gate clocks and should not be reading the
AHB clocks registers to determine their rates, as they can simply report
the output of clk_get_rate() on their parent.

Signed-off-by: Conor Dooley 
Reviewed-by: Leo Yu-Chi Liang 
Reviewed-by: Padmarao Begari

Merge tag 'u-boot-imx-20221024' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

2022-10-24T14:04:30+00:00

u-boot-imx-20221024
-------------------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/13916

- for 2022.01
- rework Kontron boards (mx6 and mx8)
- fixes for Toradex
- fixes (SPI, CAAM, )
- sync DT with Linux
- fixes for Gateworks GW7903 and GW7904 PMIC
- Engicam i.Core MX8M Plus EDIMM2.2

clk-imx8mm: Only build QSPI clocks when CONFIG_NXP_FSPI=y

2022-10-21T09:54:13+00:00

The QSPI clocks are only used when CONFIG_NXP_FSPI=y, so only build the
QSPI clocks in this case to reduce the final SPL binary size.

Signed-off-by: Fabio Estevam

clk-imx8mm: Only build ecspi clocks when CONFIG_DM_SPI=y

2022-10-21T09:54:13+00:00

The ecspi clocks are only used when CONFIG_DM_SPI=y, so only build the
ecspi clocks in this case to reduce the final SPL binary size.

Signed-off-by: Fabio Estevam

clk-imx8mm: Move CLK_ENET_AXI to the non-SPL section

2022-10-21T09:54:13+00:00

Ethernet is not used inside SPL, so move the IMX8MM_CLK_ENET_AXI clock
inside the non-SPL block to reduce the final SPL binary size.

Signed-off-by: Fabio Estevam