u-boot.git/drivers/clk, branch v2023.04

Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh

2023-03-21T15:52:55+00:00

A single reset controller driver (part of the clock driver) fix
for v2023.04 release.

clk: renesas: Pack reset identifier before look up

2023-03-20T01:46:44+00:00

The reset identifier must be processed via MOD_CLK_PACK() before it is
used to look up register and bit within reset_regs or reset_clear_regs
arrays, otherwise completely bogus register and bit is picked from the
arrays, one which may even be out of range.

Fixes: 326e05c5e21 ("clk: renesas: Add and enable CPG reset driver")
Signed-off-by: Marek Vasut

clk: rockchip: rk3568: add stubs for CLK_PCIEPHY_REF clocks

2023-03-19T06:12:00+00:00

Device tree contains assigned-clock-rates property for these,
but default value will work just fine

Reviewed-by: Kever Yang 
Signed-off-by: Vasily Khoruzhick

clk: rockchip: rk3588: Fix clk_aux16m in clock driver

2023-03-19T05:17:28+00:00

The rate and error value is not returned for aux16m clocks, fix this.

Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support")
Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang

clk: rockchip: rk3568: Fix reset handler

2023-03-19T05:17:28+00:00

The reset handler for rk3568 is missing its private data. This leads to
an abort when a reset is triggered.

  => reset
  resetting ...
  "Synchronous Abort" handler, esr 0x96000045
  elr: 0000000000a2bc04 lr : 0000000000a2bbd4 (reloc)
  elr: 00000000eff9bc04 lr : 00000000eff9bbd4
  x0 : 00000000fdd20000 x1 : 0000000014000001
  x2 : 000000000000fdb9 x3 : 00000000edf77e88
  x4 : 00000000edf50e78 x5 : 00000000edf77530
  x6 : 000000000000001d x7 : 00000000edf8a1d0
  x8 : 00000000ffffffd8 x9 : 0000000000000008
  x10: 000000000000000d x11: 0000000000000006
  x12: 000000000001869f x13: 0000000086c290c5
  x14: 000000009118e878 x15: 0000000000000000
  x16: 00000000eff9bbb8 x17: 0000000012f8c119
  x18: 00000000edf50dc0 x19: 0000000000000000
  x20: 0000000000000001 x21: 0000000000000000
  x22: 00000000edf85900 x23: 0000000000000001
  x24: 00000000effe8bbc x25: 0000000000000000
  x26: 00000000edf85940 x27: 0000000000000000
  x28: 0000000000000000 x29: 00000000edf3c8e0

  Code: d65f03c0 d5033fbf b9400661 529d9502 (b8216802)
  Resetting CPU ...

Add the missing dev_set_priv to the rk3568 clk driver to fix this.

Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Signed-off-by: Peter Geis 
Reviewed-by: Kever Yang 
Reviewed-by: Jagan Teki 
Tested-by: Jagan Teki  # radxa-cm3
Signed-off-by: Jonas Karlman

clk: renesas: Always select DM_RESET to prevent inobvious failure of rst_gen3 subdriver

2023-03-10T16:46:09+00:00

The CLK_RCAR_GEN3 registers two subdrivers, clk_gen3 and rst_gen3.
The former depends on the clock framework, which is always enabled
in this context of clock framework driver, while the later depends
on reset framework which may not always be enabled.

Ensure the reset framework is also always enabled to prevent inobvious
early boot time bind failure of the CPG driver, which leads to system
showing no activity and is difficult to debug.

Note that one possible approach to debug this is to use CONFIG_DEBUG_UART
and add debug printascii()s into the drivers/clk/renesas/clk-rcar-gen3.c .

Signed-off-by: Marek Vasut

clk: rockchip: rk3568: add more supported clk rates for sdmmc and emmc

2023-02-28T10:07:29+00:00

SDHCI driver may attempt to set 26MHz clock, but clk_rk3568
will return error in this case. Apparently, SDHCI silently ignores the
error and as a result eMMC initialization fails.

Add 25 MHz and 26 MHz clk rates for sdmmc and emmc on rk3568 to fix that.

Signed-off-by: Vasily Khoruzhick 
Reviewed-by: Kever Yang

clk: rockchip: pll: Add pll_rk3588 type for rk3588

2023-02-28T10:07:27+00:00

Add RK3588 pll set and get rate clock support.

Signed-off-by: Elaine Zhang 
Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang

clk: rockchip: Add rk3588 clk support

2023-02-28T10:07:27+00:00

Add clock driver support for Rockchip RK3588 SoC.

Signed-off-by: Elaine Zhang 
Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 
Signed-off-by: Kever Yang

clk: Allow clk_get_by_name() with NULL name

2023-02-12T18:44:20+00:00

This allows devm_clock_get(dev, NULL) to work and get the first clock,
which is common in code ported from Linux.

Signed-off-by: Samuel Holland 
Reviewed-by: Sean Anderson 
Reviewed-by: Simon Glass 
Link: https://lore.kernel.org/r/20230122000252.53642-1-samuel@sholland.org