u-boot.git/drivers/clk, branch v2023.07.01

clk: starfive: pll: Fix to use postdiv1_mask

2023-07-06T09:28:08Z

There is a problem that the rates of PLL0 and PLL1 are set incorrectly because the postdiv1_mask value is incorrectly entered when setting the pll clk reg. Modify postdiv1's mask value to be put correctly. Signed-off-by: Hoegeun Kwon Reviewed-by: Minkyu Kang

clk: sifive: only build sifive-prci.o for CONFIG_CLK_SIFIVE_PRCI

2023-07-06T09:28:08Z

If we're building non FU540/FU740 SoC drivers, then the sifive-prci.o is not needed. Only build this when CONFIG_CLK_SIFIVE_PRCI is selected. Signed-off-by: Ben Dooks Reviewed-by: Leo Yu-Chi Liang

global: Use proper project name U-Boot

2023-06-12T11:24:31Z

Use proper project name in comments, Kconfig, readmes. Reviewed-by: Neil Armstrong Acked-by: Ilias Apalodimas Reviewed-by: Stefan Roese Reviewed-by: Qu Wenruo Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/0dbdf0432405c1c38ffca55703b6737a48219e79.1684307818.git.michal.simek@amd.com

clk: zynqmp: Add fallthrough statement in the switch case

2023-06-12T11:24:31Z

Add fallthrough statement in switch case to fix the sparse warning. In function 'zynqmp_clk_get_rate': warning: this statement may fall through [-Wimplicit-fallthrough=] Signed-off-by: Algapally Santosh Sagar Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20230519113816.22083-2-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek

Merge tag 'u-boot-imx-20230525' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

2023-05-25T18:27:39Z

u-boot-imx-20230525 ------------------- - i.MX93 series - Fixes CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16412

imx: move imx8 sci header file to include/firmware/imx

2023-05-21T14:54:32Z

Move imx8 sci header file to include/firmware/imx, then we could use build macro to reuse some i.MX8 drivers for i.MX9, such as drivers/cpu/imx8_cpu.c. Signed-off-by: Peng Fan Signed-off-by: Stefano Babic

reset: rockchip: implement rk3588 lookup table

2023-05-17T09:36:18Z

The current DT bindings for the rk3588 clock use a different ID than the one that is supposed to be written to the hardware registers. Thus, we cannot use directly the id provided in the phandle, but rather use a lookup table to correctly setup the hardware. This approach has been implemented already in Linux, by commit : f1c506d152ff ("clk: rockchip: add clock controller for the RK3588") Hence, implement a similar approach using the lookup table, and adapt the existing reset driver to work with SoCs using lookup table. The file rst-rk3588.c has been copied as much as possible from Linux. Adapt the clk rk3588 driver as well to bind the reset driver with the lookup table. Reviewed-by: Kever Yang Signed-off-by: Eugen Hristev

clk: renesas: add R906G032 driver

2023-05-13T02:01:30Z

Clock driver for the Renesas RZ/N1 SoC family. This is based on Linux kernel 6.2.y drivers/clk/renesas/r9a06g032-clocks.c as found in commit 02693e11611e ("clk: renesas: r9a06g032: Repair grave increment error"), with the following additional patch series applied: https://lore.kernel.org/linux-renesas-soc/20230301215520.828455-1-ralph.siemsen@linaro.org/ Notable difference: this version avoids allocating a 'struct clk' for each clock source, as this is problematic before relocation. Instead, it uses the same approach as existing Renesas R-Car Gen2/3 clock drivers, using a temporary structure filled on-the-fly. Signed-off-by: Ralph Siemsen Reviewed-by: Marek Vasut

clk: renesas: prepare for non R-Car clock drivers

2023-05-13T02:01:30Z

Add new CONFIG_CLK_RCAR to control compilation of shared code for R-Car clock drivers (renesas-cpg-mssr.c). Enable this for R-Car Gen2 and 3. This is necessary so that CONFIG_CLK_RENESAS can be enabled, allowing recursion into the drivers/clk/reneasas directory, without bringing in the R-Car support code. The support code contains platform specific access (TMU_BASE) which is not needed on other Renesas devices such as RZ/N1. Signed-off-by: Ralph Siemsen Reviewed-by: Sean Anderson Reviewed-by: Marek Vasut

clk: rockchip: rk3588: add hardcoded assigned clocks values

2023-05-09T14:50:01Z

The CRU is being probed with a default set of assigned clocks, which are not implemented in the driver at all. Hence, when clk_set_defaults is called, it fails with ENOENT. This would not be a problem, as the CRU still handles all the required clocks, and the assigned clocks are default configs which are preprogrammed or not required for Uboot operations. However, the rockchip reset driver is being bound by the same DT node as CRU, as the reset driver has no DT node. But, when probing the reset node, it will call again the clk_set_defaults for the CRU node, and failing because of missing those specific clocks in the rk3588 clock driver. To avoid this, simply implement a basic set/get that will just return success and the default corresponding rate for the required assigned clocks. As those clocks were not supported in Uboot, not required for Uboot operations, there is no need to do any different kind of initialization. Signed-off-by: Eugen Hristev Reviewed-by: Kever Yang