u-boot.git/drivers/clk, branch v2023.10

clk: at91: Fix initializing arrays

2023-09-29T13:45:40Z

Arrays are not cleared entirely because ARRAY_SIZE returns the number of elements in an array, not the size in bytes. This commit fixes the calls to memset by providing the array size in bytes instead of the number of elements in the array. Signed-off-by: Francois Berder

Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh

2023-08-20T15:09:11Z

clk: stm32mp1: remove error for disabled clock in stm32mp1_clk_get_parent

2023-08-16T13:23:09Z

To disabled a clock in clock tree initialization for a mux of STM32MP15, the selected clock source index is set with the latest possible index for the number of bit used. Today this valid configuration cause a error in U-Boot messages, for example with CLK_ETH_DISABLED, when this clock is not needed for the used ETH PHY without crystal: no parents defined for clk id 123 This patch change the level of this message to avoid this trace for valid clock tree. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard

clk: renesas: Tear clock controller down last before booting OS

2023-08-12T22:03:36Z

Once all the other drivers got torn down in preparation for the OS to start, tear down the clock controller last. The clock controller must be torn down last as some of the clock which get turned off might have still been needed during the teardown stage of the other drivers. Signed-off-by: Marek Vasut Signed-off-by: Tam Nguyen Signed-off-by: Hai Pham

clk: rockchip: rk3308: Support reading UART rate and clock registers

2023-08-12T02:37:57Z

Add support to read RK3308 registers used to configure UART clocks, and thus to get UART rate and baudrate. This fixes clock_get_rate returning error on serial device probing. Moreover, there is no need anymore to use 'clock-frequency' property for UART nodes in *-u-boot.dtsi files for all cases where UART is not inited by U-Boot proper or by SPL o by TPL code but by a preliminary external boot phase (for Rock PI S, UART is inited by external TPL). Signed-off-by: Massimo Pegorer Reviewed-by: Kever Yang

clk: rockchip: rk3308: Fix ordering between masking and shifting

2023-08-12T02:37:57Z

As per definitions of masks and shift offsets in cru_rk3308.h, values read from registers must be first masked and then shifted. By the way, this fix is binary invariant, because in all of fixed cases the shift offset is zero. Signed-off-by: Massimo Pegorer Reviewed-by: Kever Yang

clk: rockchip: rk3568: Add dummy support for GMAC speed clocks

2023-08-12T02:35:35Z

Pine64 Quartz64 boards DT reference SCLK_GMAC1_RGMII_SPEED in the assigned-clocks property of the gmac1 node. This result in a ENOENT error when driver core tries to set a parent for this clock. The clock speed in rgmii/rmii mode is changed using clk_set_rate of the tx_rx clock and not using clk_set_parent of the speed clock. Add dummy support for SCLK_GMAC1_RGMII_SPEED and similar clocks to clk driver to allow a driver for gmac node to probe. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang

clk: rockchip: rk3568: Include UART clocks in SPL

2023-08-12T02:35:35Z

The clock driver for RK3568 does not include support for UART clocks in SPL. This result in the following message with high enough loglevel. ns16550_serial serial@fe660000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 Fix this by including support for UART clocks in SPL. Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") Signed-off-by: Jonas Karlman Reviewed-by: Eugen Hristev Reviewed-by: Kever Yang

clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div

2023-08-12T02:35:35Z

The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide, not 5 bits wide as currently defined in CPLL_25M_DIV_MASK. Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate. Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang

clk: rockchip: rk3568: Fix clk selection in rk3568_pwm_get_clk

2023-08-12T02:35:35Z

Fix use of wrong clk selection for CLK_PWM1 on RK3568. Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") Signed-off-by: Damon Ding Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang