u-boot.git/drivers/clk, branch v2024.04

clk: clk-imx8qm: Add LPUART IPG entries

2024-03-22T15:10:39Z

Since commit cc7df0b9e8bc ("serial: lpuart: Enable IPG clock") the apalis-imx8qm board no longer boots. The reason is that the imx8qm clock driver does not handle the LPUART IPG clocks inside get_rate(), set_rate() and enable() functions. Fix the boot regression by adding the LPUART IPG entries. Fixes: cc7df0b9e8bc ("serial: lpuart: Enable IPG clock") Reported-by: Marcel Ziswiler Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan

clk: clk-imx8qxp: Add LPUART IPG entries

2024-03-22T15:10:39Z

Since commit cc7df0b9e8bc ("serial: lpuart: Enable IPG clock") the colibri-imx8qxp board no longer boots. The reason is that the imx8qxp clock driver does not handle the LPUART IPG clocks inside get_rate(), set_rate() and enable() functions. Fix the boot regression by adding the LPUART IPG entries. Fixes: cc7df0b9e8bc ("serial: lpuart: Enable IPG clock") Reported-by: Marcel Ziswiler Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan Tested-by: Hiago De Franco # Toradex Colibri iMX8X Acked-by: Sean Anderson

Merge patch series "ARM: renesas: Rename R-Mobile to Renesas"

2024-03-02T19:30:25Z

Marek Vasut says: Rename R-Mobile to Renesas all over the place because the chips are made by Renesas, while only a subset of them is from the R-Mobile line.

ARM: renesas: Rename ARCH_RMOBILE to ARCH_RENESAS

2024-03-02T19:29:36Z

Rename ARCH_RMOBILE to ARCH_RENESAS because all the chips are made by Renesas, while only a subset of them is from the R-Mobile line. Use the following command to perform the rename: " $ git grep -l 'ARCH_RMOBILE' | xargs -I {} sed -i 's@ARCH_RMOBILE@ARCH_RENESAS@g' {} " Signed-off-by: Marek Vasut Reviewed-by: Paul Barker

clk: renesas: Confirm all clock & reset changes on RZ/G2L

2024-02-28T17:42:27Z

When enabling/disabling a clock or reset signal, confirm that the change has completed before returning from the function. A somewhat arbitrary 100ms timeout is defined to ensure that the system doesn't lock up in the case of an error. Since we need to dynamically determine if we're waiting for a 0 bit or a 1 bit, it's easier to use wait_for_bit_32() than readl_poll_timeout(). This change is needed for reliable initialization of the I2C driver which is added in a following patch. Signed-off-by: Paul Barker Reviewed-by: Marek Vasut

Merge https://gitlab.denx.de/u-boot/custodians/u-boot-samsung

2024-02-20T13:02:49Z

clk: renesas: Fix broken clocks on all Gen2 boards

2024-02-17T21:38:18Z

To prepare support for multiple register layouts pointers to register tables where added to struct cpg_mssr_info. These pointers are suppose to be filled in at probe time and no intended change in behavior was intended. However the new pointers where only filled in by some paths of the driver implemented in clk-rcar-gen3.c. The path implemented in clk-rcar-gen2.c was not updated leaving the pointers uninitialized leading to a crash when trying to probe the clocks. Fix this by filling in the pointers in the Gen2 code path with the values used before they where moved to struct cpg_mssr_info. Fixes: d413214fb748 ("clk: renesas: Add register pointers into struct cpg_mssr_info") Signed-off-by: Niklas Söderlund Acked-by: Marek Vasut Tested-by: Marek Vasut # R8A7791 Porter Reviewed-by: Geert Uytterhoeven

clk: renesas: Implement R8A779H0 V4M PLL7 support

2024-02-10T16:08:06Z

Add PLL7 support to Gen3/Gen4 common clock driver. Add initial PLL7 multiplier and divider values into table in R8A779H0 V4M clock driver. The PLL7 is new PLL added in R8A779H0 V4M SoC. Only integer multiplication mode is supported by PLL7. The PLL reference clock are either 16.66 MHz or 20 MHz on R8A779H0 V4M SoC, and the output frequency must be 2000 MHz. The multiplier values fitting this requirement are calculated to 120 or 100. Signed-off-by: Marek Vasut

clk: renesas: Add R8A779H0 V4M clock tables

2024-02-10T16:08:06Z

Add clock tables for R8A779H0 V4M SoC. The current version is imported from: https://lore.kernel.org/linux-renesas-soc/c678ef7164e3777fa91572f72e47ef385cea64b8.1706194617.git.geert+renesas@glider.be/ The current version still contains PLL7 extras from the previous version to provide ethernet support in U-Boot. Signed-off-by: Hai Pham

clk: clk-gpio: add actual gated clock

2024-01-30T03:35:34Z

Existing gpio-gate-clock driver acts like a simple GPIO switch without any effect on gated clock. Add actual clock actions into enable/disable ops and implement get_rate op by passing gated clock if it is enabled. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Sean Anderson Link: https://lore.kernel.org/r/20240110160956.4476-2-clamor95@gmail.com [ sorted includes ] Signed-off-by: Sean Anderson