u-boot.git/drivers/clk, branch v2024.07

clk: rockchip: rk3588: Set SPLL frequency during SPL stage

2024-05-24T09:58:59+00:00

All parts expect the SPLL to run at 702MHz. In U-Boot it's the SPLL_HZ
declaring this rate and in the kernel it's a fixed clock definition.

While everything is expecting 702MHz, the SPLL is not running that
frequency when coming from the bootrom though, instead it's running
at 351MHz and the vendor-u-boot just sets it to the expected frequency.

The SPLL itself is located inside the secure-BUSCRU and in theory
accessible as an SCMI clock, though this requires an unknown amount
of cooperation from trusted-firmware to set at a later stage, though
during the SPL stage we can still access the relevant CRU directly.

The SPLL is for example necessary for the DSI controllers to produce
output.

As the SPLL is "just" another rk3588 pll, just set the desired rate
directly during the SPL stage.

Tested on rk3588-rock5b and rk3588-tiger by reading back the PLL rate
and also observing working DSI output with this change.

Fixes: 6737771600d4 ("rockchip: rk3588: Add support for sdmmc clocks in SPL")
Suggested-by: Andy Yan 
Signed-off-by: Heiko Stuebner 
Cc: Jonas Karlman 
Cc: Quentin Schulz 
Reviewed-by: Kever Yang

Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""

2024-05-19T14:16:36+00:00

When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman 
Signed-off-by: Tom Rini

Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"

2024-05-13T15:15:51+00:00

Roger Quadros  says:

Sync AM62 device tree files with Linux v6.9 and
add in the missing bits in -u-boot.dtsi to get CPSW
Ethernet working.

CI testing: https://github.com/u-boot/u-boot/pull/534

Merge patch series "arm: Add Analog Devices SC5xx Machine Type"

2024-05-08T01:24:07+00:00

Greg Malysa  says:

This series adds support for the ADI SC5xx machine type and includes two
core drivers that are required for being able to boot any board--a UART
driver, the gptimer driver which is used as a clock reference (CNTVCNT
is not supported on the armv7 sc5xx SoCs) and the clock tree driver. Our
corresponding Linux support relies on u-boot configuring the clocks
correctly before booting, so it is not possible to boot any board
without the CGU/CDU configuration happening here. There are also no
board files, device trees, or defconfigs included here, but some common
definitions that will be used to build board files currently are. The
sc5xx SoCs themselves include many armv7 families (sc57x, sc58x, and
sc594) all using an ARM Cortex-A5, and one armv8 family (sc598) indended
to be a drop-in replacement for the SC594 in terms of peripherals, with
a Cortex-A55 instead.

Some of the configuration code in dmcinit and clkinit is quite scary and
causes a lot of checkpatch violations. It is modified from code
initially provided by ADI, but it has not been fully rewritten. There's
a question of how important it is to clean up this code--it has some
quality violations, but it has been in use (including in production) for
over two years and is known to work for performing the low level SoC
initialization, while a rewrite might introduce timing or sequence bugs
that could take a significant amount of time to detect in the future.

drivers: clk: adi: Add in SC5XX-family clock driver

2024-05-08T01:24:00+00:00

This adds support for the SC5XX clock trees which are required for reading
clock speeds on the SoCs. This is largely a port of the same support for
Linux, which has not yet been submitted upstream.

Co-developed-by: Greg Malysa 
Signed-off-by: Greg Malysa 
Co-developed-by: Ian Roberts 
Signed-off-by: Ian Roberts 
Signed-off-by: Vasileios Bimpikas 
Signed-off-by: Utsav Agarwal 
Signed-off-by: Arturs Artamonovs 
Signed-off-by: Nathan Barrett-Morrison

clk: Remove and add needed includes

2024-05-07T14:00:41+00:00

Remove  from this driver directory and when needed
add missing include files directly.

Signed-off-by: Tom Rini

clk: rockchip: rk3328: Add SCLK_USB3OTG_REF support

2024-05-07T07:56:10+00:00

The SCLK_USB3OTG_REF clocks is used as reference clock for USB3 block.

Add simple support to get rate of SCLK_USB3OTG_REF clocks to fix
reference clock period configuration.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang

clk: rockchip: rk3399: Add SCLK_USB3OTGx_REF support

2024-05-07T07:56:09+00:00

The SCLK_USB3OTGx_REF clocks is used as reference clock for USB3 block.

Add simple support to get rate of SCLK_USB3OTGx_REF clocks to fix
reference clock period configuration.

Also replace use of 24000000 with the OSC_HZ constant.

Signed-off-by: Jonas Karlman 
Reviewed-by: Quentin Schulz 
Reviewed-by: Kever Yang

clk: rockchip: rk3399: Improve support for SCLK_PCIEPHY_REF clock

2024-05-07T07:56:09+00:00

rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the
SCLK_PCIEPHY_REF clock.

The existing enable/disable ops for SCLK_PCIEPHY_REF currently force
use of 24 MHz parent and rate.

Add improved support for setting parent and rate of the pciephy refclk
to driver to better support assign-clock props for pciephy refclk in DT.

This limited implementation only support setting 24 or 100 MHz rate,
and expect npll and clk_pciephy_ref100m divider to use default values.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang

clk: rockchip: rk3399: Add dummy support for ACLK_VDU clock

2024-05-07T07:56:08+00:00

rk3399.dtsi from linux v5.19 and newer try to set VDU clock rate to
400 MHz using an assigned-clock-rates prop of the CRU node.

U-Boot does not use or need this clock so add dummy support for getting
and setting ACLK_VDU clock rate to allow CRU driver to be loaded with an
updated rk3399.dtsi.

Signed-off-by: Jonas Karlman 
Reviewed-by: Kever Yang