u-boot.git/drivers/clk, branch v2024.10

clk: renesas: rcar-gen3: Fix SSCG caching replacement with MDSEL/PE caching

2024-10-05T19:15:22Z

The SSCG is active with MDSEL[12] is not set. Previous commit 99c7e031196d ("clk: renesas: rcar-gen3: Replace SSCG caching with MDSEL/PE caching") inverted the conditional assignment of priv->sscg = !(cpg_mode & BIT(12)) during conversion from (priv->sscg ? 16 : 0) to priv->cpg_mode & BIT(core->offset) ? 16 : 0; Invert the assignment back to the correct state. This fixes R8A77980, R8A77990, R8A77995 and R8A774C0. Fixes: 99c7e031196d ("clk: renesas: rcar-gen3: Replace SSCG caching with MDSEL/PE caching") Signed-off-by: Marek Vasut

clk: sifive: avoid declaring static variables in includes

2024-09-10T02:10:43Z

The existing code is unnecessarily convoluted: Arrays __prci_init_clocks_fu[5|7]40 are initialized with data. In separate includes fu[5|7]40-prci.h the size of the arrays is provided as constants. By moving the structures prci_clk_fu[5|7]40 to the respective code modules we can directly use ARRAY_SIZE() to access the size of the data used for initialization. Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang

clk: sifive: append missing \n to messages

2024-09-10T02:10:43Z

If multiple messages are written, line-feeds improve the readability. Fixes: c40b6df87fc0 ("clk: Add SiFive FU540 PRCI clock driver") Signed-off-by: Heinrich Schuchardt Reviewed-by: Sean Anderson

clk: zynqmp: Add set_rate support for display clocks

2024-08-05T14:10:36Z

If "assigned-clock-rates" property is included in the device tree, display driver probe is getting failed, as dp_video_ref till dp_stc_ref clocks are missing from set rate function, adding them to fix the probe failure. Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20240711082939.29260-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek

clk: imx8m: register ARM A53 core clock

2024-08-02T18:16:51Z

Register ARM A53 core clock for i.MX 8M Mini, Nano and Plus, preparing for enabling the 'cpu' command, which depends on this to print CPU core frequency. Signed-off-by: Hou Zhiqiang

clk: clk-uclass: Print clk name in clk_enable/clk_disable

2024-08-01T21:35:28Z

Print clk name in clk_enable and clk_disable. Make sense to know what clock get disabled/enabled before a system crash or system hang. Signed-off-by: Michael Trimarchi

clk: Fix error message in clk_get_bulk

2024-08-01T21:33:14Z

Fix a logical inversion of the printed text. Signed-off-by: Jan Kiszka Reviewed-by: Sam Protsenko Reviewed-by: Sean Anderson

Merge patch series "clk: mediatek: add OPs to support OF_UPSTREAM"

2024-08-01T21:32:54Z

Christian Marangi says: This series doesn't currently change anything and it does add all the additional OPs to make support of OF_UPSTREAM. While converting the mt7681/7686/7688/7623/7622 it was notice lots of discrepancy between the downstream dtsi and the upstream one and the clock ID between downstream clock ID and upstream clock ID. Upstream reference clock by names and clock are handled by the CCF (Common Clock Framework). The same can't be used here as we would quickly reach the max space allocated before relocation. The current mediatek clock driver reference all the parents and clocks with offset from the clk ID related to the different tables. Discrepancy between clock ID and the order in the clocks table cause one clock referenced for another or even crash for trying to access a clock at an offset that doesn't exist. To handle this and permit use of OF_UPSTREAM, various measure and changes are done to the mediatek clock driver to support it. This series have all the generic clock changes. Once this is merged, series for each SoC will came that will just change files in their dedicated clock driver. This is to prevent massive patch and to permit to split series, one for each SoC. As said at the start, these changes doesn't cause regression and are just expansion to the current API. Current behaviour is saved in every possible way (aside from the first 2 patch that fixes latent bugs)

clk: mediatek: add support for APMIXED parent in infra MUX

2024-08-01T21:32:18Z

Add support for APMIXED parent in infra MUX. This is the case for mt7622 that reference APMIXED parents for the MUX1_SEL clock. We assume the second level parent is always APMIXED. Signed-off-by: Christian Marangi

clk: mediatek: add support for GATEs for APMIXED OPs

2024-08-01T21:32:18Z

Add support for GATEs for APMIXED OPs. It's possible that some APMIXED have also gates on top of PLL. This is the case for mt7622. Add support for this. Signed-off-by: Christian Marangi