Early revisions of the R-Car V4M Series Hardware User’s Manual
contained an incorrect formula for the CPU core clocks:
ZCnφ = (PLL2VCO x 1/2) x mult/32
Dang-san fixed this by using CLK_PLL2_DIV2 instead of CLK_PLL2 as the
parent clock.
In Rev.0.70 of the documentation, the formula was corrected to:
ZCnφ = (PLL2VCO x 1/4) x mult/32
As the CPG Block Diagram now shows a separate 1/4 post-divider for PLL2,
the use of CLK_PLL2_DIV2 is a recurring source of confusion. Hence get
rid of CLK_PLL2_DIV2, and include the proper 1/4 post-divider in the
invocation of the DEF_GEN4_Z() macro, like is done on other R-Car Gen4
(and Gen3) SoCs.
Ported from Linux commit
92850bed9d4d ("clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks")
Reported-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/0d2789cac2bf306145fe0bbf269c2da5942bb68f.1728377724.git.geert+renesas@glider.be
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
In case DM drivers probe earlier than board clock setup is done init of basic clocks should be done in CAR driver probe as well. Add it to avoid possible clock related problems. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Return PLL id into struct clk if PLL is parsed from device tree instead of throwing an error. Allow requesting PLL clock rate via get_rate op. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Cosmetic change. Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
The correct spelling is R-Car, including the dash, update the usage. Kconfig strings and comment changes only, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
In the RZ/G2L family, core clocks are always on and can't be disabled. However, drivers which are shared with other SoCs may call clk_enable() or clk_enable_bulk() for a clock referenced in the device tree which happens to be a core clock on the RZ/G2L. To avoid the need for conditionals in these drivers, simply ignore attempts to enable a core clock. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This breaks chromebook_coral which says: Video: No video mode configured in FSP! This reverts commit 2e9313179a846b581c0fc3f6a49e19f3d343efa8. Signed-off-by: Simon Glass <sjg@chromium.org>
In case lists_driver_lookup_name("rst_gen3") fails, the clk_gen3 driver
has to be unbound before erroring out. Reorder the function such that
both clk_gen3 and rst_gen3 drivers are looked up first, if either look
up fails then the function errors out right away. Second, the clk_gen3
is bound, if binding fails, the function still errors out right away
because there is nothing to undo after either lists_driver_lookup_name()
call. Finally, rst_gen3 is bound and if this binding fails, then that
is the only place where clk_gen3 has to be unbound before erroring out.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Why get a devicetree description wrong once when you can get it wrong twice? The original mistake, which the driver supports was failing to describe the main PLL that the "cfg" and "periph" clocks parented by. The second mistake was describing the "cfg" and "periph" clocks a reg region within the clock controller, rather as two registers within a syscon region that also contains pinctrl, interrupt muxing controls and other functions. Make up for lost time and describe these regions as they should have been originally, preserving support for the existing two configurations for the sake of existing systems with firmware-provided devicetrees. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/22993
- New boards:
rk3566: Hardkernel ODROID-M1S
rk3588s: Hardkernel ODROID-M2
rk3588: NanoPC-T6 LTS
- Migrate to use USB_DWC3_GENERIC for rk3328
- Other board level config and dts update