u-boot.git/drivers/clk, branch v2025.07

clk: qcom: apq8016: Fix SDCC clock warnings

2025-06-02T16:20:16Z

As of commit dc8754e8e408 ("clk/qcom: apq8016: improve clk_enable logging") there are now warnings in the U-Boot console on DragonBoard 410c: apq8016_clk_enable: unknown clk id 122 apq8016_clk_enable: unknown clk id 123 apq8016_clk_enable: unknown clk id 124 apq8016_clk_enable: unknown clk id 125 This is because we don't implement enable() properly for the SDCC clocks. Currently they are being enabled as part of set_rate(). Fix this by moving the enable calls out of the apq8016_clk_init_sdc() function and convert them to the equivalent GATE_CLK_POLLED() definitions. Reviewed-by: Neil Armstrong Signed-off-by: Stephan Gerhold Reviewed-by: Sumit Garg Reviewed-by: Casey Connolly Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-6-fcc371c9e45f@linaro.org Signed-off-by: Casey Connolly

clk: qcom: apq8016: Convert GATE_CLK() to GATE_CLK_POLLED()

2025-06-02T16:20:15Z

Convert the usages of GATE_CLK() in clock-apq8016 to GATE_CLK_POLLED() to make sure that we poll the status when enabling clocks: - PRNG_AHB_CLK is a vote clock, so we poll a different register address. - The USB clocks are simple branches, so enable/poll is the same register. Reviewed-by: Neil Armstrong Signed-off-by: Stephan Gerhold Reviewed-by: Sumit Garg Reviewed-by: Casey Connolly Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-5-fcc371c9e45f@linaro.org Signed-off-by: Casey Connolly

clk: qcom: Allow polling for clock status in qcom_gate_clk_en()

2025-06-02T16:20:15Z

GATE_CLK() in its current state is unsafe: A simple write to the clock enable register does not guarantee that the clock is immediately running. Without polling the clock status, we may issue writes to registers before the necessary clocks start running. This doesn't seem to cause issues in U-Boot at the moment, but for example removing the CLK_OFF polling in TF-A for the SMMU clocks on DB410c reliably triggers an exception during boot. Make it possible to poll the branch clock status register, by adding a new GATE_CLK_POLLED() macro that takes the extra register address. Existing usages work just as before, without polling the clock status. Ideally all usages should be updated to specify the correct poll address in the future. The Qualcomm naming for these clocks is "branch" and not "gate", but let's keep the existing naming for now to avoid confusion until all others drivers have been converted. Reviewed-by: Neil Armstrong Signed-off-by: Stephan Gerhold Reviewed-by: Sumit Garg Reviewed-by: Casey Connolly Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-4-fcc371c9e45f@linaro.org Signed-off-by: Casey Connolly

clk: qcom: Use setbits_le32() for qcom_gate_clk_en()

2025-06-02T16:20:15Z

The other clock enable functions in clock-qcom.c use setbits_le32() to read/modify/write the enable registers. Use the same for qcom_gate_clk_en() to simplify the code a bit. Reviewed-by: Neil Armstrong Signed-off-by: Stephan Gerhold Reviewed-by: Sumit Garg Reviewed-by: Casey Connolly Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-3-fcc371c9e45f@linaro.org Signed-off-by: Casey Connolly

clk: qcom: Move qcom_gate_clk_en() to C file

2025-06-02T16:20:15Z

This avoids having to inline it separately into every single clock driver, when U-Boot is built with support for multiple SoCs. Reviewed-by: Neil Armstrong Signed-off-by: Stephan Gerhold Reviewed-by: Sumit Garg Reviewed-by: Casey Connolly Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-2-fcc371c9e45f@linaro.org Signed-off-by: Casey Connolly

clk: qcom: apq8016: Fix SDCC clock addresses

2025-06-02T16:20:15Z

The SDCC_...(n) macros in clock-apq8016.c result in the wrong addresses: - SDCC1: SDCC_APPS_CBCR(0) = ((0 * 0x1000) + 0x41018) = 0x41018 Should be 0x42018, this is an invalid register close to the USB clocks. - SDCC2: SDCC_APPS_CBCR(1) = ((1 * 0x1000) + 0x41018) = 0x42018 Should be 0x43018, this is the SDCC1 clock. When we try to enable SDCC2, we actually end up enabling SDCC1. When we try to enable SDCC1, we just issue some broken register writes. This hasn't caused any trouble so far, because the boot firmware is keeping both SDCC clocks running. However, if these clocks are disabled when entering U-Boot, MMC initialization is failing. Fix this by using the proper offset for the macros. The SDCC_CMD_RCGR() was already correct, but change it the same way for consistency. Fixes: 085921368b7d ("arm: Add support for Qualcomm Snapdragon family") Reviewed-by: Neil Armstrong Signed-off-by: Stephan Gerhold Reviewed-by: Sumit Garg Reviewed-by: Casey Connolly Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-1-fcc371c9e45f@linaro.org Signed-off-by: Casey Connolly

clk: thead: Port clock controller driver of TH1520 SoC

2025-05-21T08:49:57Z

The driver is adapted from Linux kernel's version of clk-th1520-ap.c, with only output clocks for external sensors, which are barely useful in bootloaders, removed. Same as the mainline driver, it currently lacks of ability to enable and reconfigure PLLs, which could be implemented later. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang

spi: fspi: Add imxrt1170 device data

2025-05-12T21:42:53Z

Add the device specific driver data, and the clock configuration. Signed-off-by: Jonathan Currier

clk: Fix clk_set_parent() regression

2025-05-12T14:04:51Z

The commit ac30d90f3367 ("clk: Ensure the parent clocks are enabled while reparenting") add a call to clk_enable() for the parent clock. For clock drivers that do not implement the enable() ops, like most Rockchip clock drivers, this now cause the set_parent() ops to never be called when CLK_CCF=n (default for Rockchip). clk_enable() typically return -ENOSYS when the enable() ops is not implemented by the clock driver, with CLK_CCF=y clk_enable() instead return 0 when the enable() ops is unimplemented. Change to ignore -ENOSYS from the newly introduced clk_enable() call to fix this regression and restore the old behavior of set_parent() ops being called regardless of if enable() ops is implemented or not. Fixes: ac30d90f3367 ("clk: Ensure the parent clocks are enabled while reparenting") Signed-off-by: Jonas Karlman Tested-by: Dang Huynh Acked-by: Miquel Raynal

clk: scmi: check the clock state/parent/rate control permissions

2025-05-03T19:55:32Z

Clock driver based on SCMI clock management protocol in Linux checks clock state, parent and rate control permissions. To be consistent with the kernel driver, add this check here. CLOCK_GET_PERMISSIONS is from ARM System Control and Management Interface Platform Design Document 3.2. When using common clock framework (CCF), use the clock signal ID to get the clock registered by clk_register() in scmi_clk_probe(), and then obatin the struct clk_scmi variable with container_of(). Signed-off-by: Alice Guo Signed-off-by: Ye Li Reviewed-by: Peng Fan