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<title>u-boot.git/drivers/clk, branch v2025.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/clk?h=v2025.10</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/clk?h=v2025.10'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2025-10-04T18:51:01Z</updated>
<entry>
<title>clk: ti: fix K3 clock driver help texts</title>
<updated>2025-10-04T18:51:01Z</updated>
<author>
<name>Yegor Yefremov</name>
<email>yegorslists@googlemail.com</email>
</author>
<published>2025-09-22T13:27:00Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c23688d0533db87c533e415be7809b435080c7e4'/>
<id>urn:sha1:c23688d0533db87c533e415be7809b435080c7e4</id>
<content type='text'>
Add "in SPL" to the SPL related driver help texts.

Signed-off-by: Yegor Yefremov &lt;yegorslists@googlemail.com&gt;
Reviewed-by: Quentin Schulz &lt;quentin.schulz@cherry.de&gt;
</content>
</entry>
<entry>
<title>clk: stm32: Pass udevice pointer to clk_register_composite()</title>
<updated>2025-09-16T13:24:30Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut@mailbox.org</email>
</author>
<published>2025-09-06T23:00:01Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7b9b34aa6d2a9125adca5a286eca4bda87e215b9'/>
<id>urn:sha1:7b9b34aa6d2a9125adca5a286eca4bda87e215b9</id>
<content type='text'>
The clk_register_composite() does clk_resolve_parent_clk() look up,
which requires valid udevice pointer. Do not pass NULL, pass a valid
device pointer to prevent hang on registering ck_usbo_48m clock on
STM32MP13xx.

Signed-off-by: Marek Vasut &lt;marek.vasut@mailbox.org&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-samsung</title>
<updated>2025-09-05T14:15:16Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2025-09-05T14:15:16Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=328747974a0620d0996113fe2b3906b06e96de00'/>
<id>urn:sha1:328747974a0620d0996113fe2b3906b06e96de00</id>
<content type='text'>
- Fix issues reported by smatch
- exynos4210-origen cleanups
- e850-96 improvements
</content>
</entry>
<entry>
<title>clk: exynos: Fix always true test</title>
<updated>2025-09-01T07:37:08Z</updated>
<author>
<name>Andrew Goodbody</name>
<email>andrew.goodbody@linaro.org</email>
</author>
<published>2025-07-23T16:04:41Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c901732558fbee5b798bb7a065f7832d3a6bbc84'/>
<id>urn:sha1:c901732558fbee5b798bb7a065f7832d3a6bbc84</id>
<content type='text'>
In exynos7420_peric1_get_rate the variable ret is declared as an
'unsigned int' but is then used to receive the return value of
clk_get_by_index which returns an int. The value of ret is then tested
for being less than 0 which will always fail for an unsigned variable.
Fix this by declaring ret as an 'int' so that the test for the error
condition is valid.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody &lt;andrew.goodbody@linaro.org&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
</entry>
<entry>
<title>rockchip: clk: clk_rk3528: Add dummy CLK_REF_PCIE_INNER_PHY support</title>
<updated>2025-08-30T15:26:08Z</updated>
<author>
<name>Jonas Karlman</name>
<email>jonas@kwiboo.se</email>
</author>
<published>2025-07-30T23:52:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=281c66f39b0e6b3b520976ad0535939141f148b8'/>
<id>urn:sha1:281c66f39b0e6b3b520976ad0535939141f148b8</id>
<content type='text'>
Add dummy support for the CLK_REF_PCIE_INNER_PHY clock to allow probe of
the phy-rockchip-naneng-combphy driver on RK3528.

Signed-off-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>rockchip: clk: clk_rk3576: Add dummy CLK_REF_PCIEx_PHY support</title>
<updated>2025-08-30T15:01:44Z</updated>
<author>
<name>Jonas Karlman</name>
<email>jonas@kwiboo.se</email>
</author>
<published>2025-08-01T20:43:37Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2a6039a20994c192edb6786fa97714180bd663cf'/>
<id>urn:sha1:2a6039a20994c192edb6786fa97714180bd663cf</id>
<content type='text'>
Add dummy support for the CLK_REF_PCIEx_PHY clocks to allow probe of the
phy-rockchip-naneng-combphy driver on RK3576.

Signed-off-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-at91-fixes-2025.10-a' of https://source.denx.de/u-boot/custodians/u-boot-at91</title>
<updated>2025-08-26T14:30:21Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2025-08-26T14:30:21Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=349cf24859b5e169a441d975fb4484d8597964bc'/>
<id>urn:sha1:349cf24859b5e169a441d975fb4484d8597964bc</id>
<content type='text'>
First set of u-boot-at91 fixes for the 2025.10 cycle:

This set includes smatch fixes for clocks and mmc and one QSPI fix.
</content>
</entry>
<entry>
<title>clk: at91: Fix use of unsigned loop index</title>
<updated>2025-08-13T09:59:36Z</updated>
<author>
<name>Andrew Goodbody</name>
<email>andrew.goodbody@linaro.org</email>
</author>
<published>2025-07-23T14:13:49Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=da13ce8a6b1a37c49d2215ef78ee7984bae1c068'/>
<id>urn:sha1:da13ce8a6b1a37c49d2215ef78ee7984bae1c068</id>
<content type='text'>
The use of the unsigned variable 'i' as a loop index leads to the test
for i being non-negative always being true. Instead declare 'i' as an
int so that the for loop will terminate as expected.
If the original for loop completes 'i' will be 1 past the end of the
array so decrement it in the subsequent error path to prevent an out of
bounds access occurring.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody &lt;andrew.goodbody@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk: at91: Fix testing of unsigned variable to be negative</title>
<updated>2025-08-13T09:59:36Z</updated>
<author>
<name>Andrew Goodbody</name>
<email>andrew.goodbody@linaro.org</email>
</author>
<published>2025-07-23T14:13:48Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=29ea990a1c4a2455f432d5e71b217e93b406fc12'/>
<id>urn:sha1:29ea990a1c4a2455f432d5e71b217e93b406fc12</id>
<content type='text'>
The variable 'index' is declared as unsigned but used to receive the
return value of a function returning 'int'. This value is then tested
for being less than zero to detect an error condition but as index is
unsigned this can never be true. Change the variable 'index' to be an
int so that the error condition can be detected.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody &lt;andrew.goodbody@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-socfpga-next-20250808' of https://source.denx.de/u-boot/custodians/u-boot-socfpga</title>
<updated>2025-08-08T17:13:41Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2025-08-08T17:13:41Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=83ce0b483c1680cb39565a9d91c6ef113a309c38'/>
<id>urn:sha1:83ce0b483c1680cb39565a9d91c6ef113a309c38</id>
<content type='text'>
This pull request introduces initial U-Boot support for Agilex7 M-series, along
with several enhancements and cleanups across existing Agilex platforms. Key
changes include new board support, DDR driver additions, updated device trees,
and broader SoCFPGA SPL improvements.

Highlights:

- Agilex7 M-series bring-up:
  - Basic DT support and board initialization for Agilex7 M-series SoC and
    SoCDK.
  - New sdram_agilex7m DDR driver with UIBSSM mailbox support and HBM support.
  - Clock driver support for Agilex7 M-series.
  - New defconfig: socfpga_agilex7m_defconfig.
- Agilex and Agilex5 enhancements:
  - Improved SPL support: ASYNC interrupt enabling, system manager init
    refactor, and cold scratch register usage.
  - Updated firewall probing and watchdog support in SPL.
  - Cleaned up DDR code, added secure region support for ATF, and improved warm
    reset handling.
- Device Tree and config updates:
  - Migration to upstream Linux DT layout for Agilex platforms.
  - Consolidated socfpga_agilex_defconfig and removed deprecated configs.
  - Platform-specific environment variables for Distro Boot added.
- Driver fixes and cleanups:
  - dwc_eth_xgmac and clk-agilex cleanup and improvements.
  - Several coverity and style fixes.

Contributions in this PR are from Alif Zakuan Yuslaimi, Tingting Meng, and
Andrew Goodbody.  This patch set has been tested on Agilex 5 devkit, Agilex
devkit and Agilex7m devkit.

Passing all pipeline tests at SoCFPGA U-boot custodian
https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27318
</content>
</entry>
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