u-boot.git/drivers/clk, branch v2026.04

clk: qcom: qcs615: Add GCC_AHB2PHY_WEST_CLK clock support

2026-03-24T10:34:58Z

Add GCC_AHB2PHY_WEST_CLK gate clock definition to the QCS615 clock driver. This clock is required for proper PHY operation and eliminates clock-related warnings during USB initialization. Signed-off-by: Balaji Selvanathan Reviewed-by: Sumit Garg Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260213-talos_usb-v1-2-4c4355d61437@oss.qualcomm.com Signed-off-by: Casey Connolly

clk: qcom: qcs615: Add GCC_USB3_PRIM_CLKREF_CLK support

2026-03-24T10:34:58Z

Add support for GCC_USB3_PRIM_CLKREF_CLK to the QCS615 clock driver. This clock is referenced in the device tree USB node but was not implemented in U-Boot, causing "Clock 152 not found" warnings during fastboot run. Signed-off-by: Balaji Selvanathan Reviewed-by: Sumit Garg Link: https://patch.msgid.link/20260213-talos_usb-v1-1-4c4355d61437@oss.qualcomm.com Signed-off-by: Casey Connolly

clk: mediatek: mt7622: fix infracfg and pericfg clock operations

2026-03-17T18:51:45Z

The MT7622 infracfg and pericfg drivers both use mtk_common_clk_infrasys_init() for probe, which populates struct mtk_clk_priv and stores gate definitions in the clk_tree. However, both drivers were incorrectly wired to mtk_clk_gate_ops which expects struct mtk_cg_priv with separately populated gates/num_gates/gates_offs fields from mtk_common_clk_gate_init(). Since those fields were never set, any attempt to enable an infracfg or pericfg gate clock (e.g. CLK_INFRA_TRNG) would fail with -EINVAL. Switch both to mtk_clk_infrasys_ops and struct mtk_clk_priv to match the init function. Fixes: 72ab603b201 ("clk: mediatek: add driver for MT7622") Signed-off-by: Daniel Golle Reviewed-by: David Lechner Signed-off-by: David Lechner

treewide: Remove Timesys from ADI ADSP maintenance

2026-03-04T20:25:27Z

After years of developing the ADI ADSP platform, Timesys was purchased by another company and is no longer contracted to maintain the platform. Signed-off-by: Philip Molloy Reviewed-by: Greg Malysa

clk: stm32mp21: Add clock driver support

2026-02-24T16:39:34Z

Add clock driver support for STM32MP21 SoCs. Signed-off-by: Nicolas Le Bayon Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay

drivers/clk/clk_zynqmp.c: get rid of compiler warning for !CONFIG_CMD_CLK builds

2026-02-10T08:27:48Z

When built without CONFIG_CMD_CLK, we get a warning about the unused clk_names variable: ../drivers/clk/clk_zynqmp.c:153:27: warning: ‘clk_names’ defined but not used [-Wunused-const-variable=] 153 | static const char * const clk_names[clk_max] = { So also guard it with CONFIG_CMD_CLK to get rid of that. Signed-off-by: Peter Korsgaard Reviewed-by: Quentin Schulz Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20260119095437.2775081-2-peter@korsgaard.com

drivers/clk/Kconfig: fix "related" typo in help text

2026-02-10T08:27:48Z

It looks like the original zynqmp typo was copied to versal as well. Fix both. Signed-off-by: Peter Korsgaard Reviewed-by: Quentin Schulz Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20260119095437.2775081-1-peter@korsgaard.com

clk: sunxi: Add MBUS Master Clock Gating Register

2026-02-03T20:45:14Z

Add MBUS Master Clock Gating Register for H6 and H616 For H6/H616, the NAND controller needs the MBUS NAND clock along with CLK_NAND0/1 and CLK_BUS_NAND. The bit locations are from H6/H616 User Manuals. Signed-off-by: Richard Genoud Signed-off-by: Michael Trimarchi

clk: stm32: Update clock management for STM32MP13/25

2026-01-29T09:47:57Z

During clock's registration, clock's name are used to establish parent - child relation. On STM32MP13 and STM32MP25, most of SCMI clocks are parent clocks. Since commit fdb1bffe2827 ("clk: scmi: Postpone clock name resolution"), all scmi clocks are named by default "scmi-%zu" until they are enabled, it breaks clocks registration and boot process for STM32MP13/25 platforms. Rework the STM32 core clock driver and STM32MP13/25 clock description to use clock index instead of their real name. Introduce struct clk_parent_data which allows to identify parent clock either by index or by name. Name is only used for particular clocks provided by IP which are clock provider as i2s/i2s_ckin, usb0/ck_usbo_48m, and ltdc/ck_ker_ltdc. STM32_GATE() and STM32_COMPOSITE_NOMUX macros are updated in order to use parent clock index. As STM32MP13 supports both SPL and SCMI boot, keep using an array with clock's name for SPL. Fixes: fdb1bffe2827 ("clk: scmi: Postpone clock name resolution") Reviewed-by: Patrick Delaunay Signed-off-by: Patrice Chotard

clk: stm32mp13: Reorder include files

2026-01-29T09:47:57Z

Reorder include following rules available here : https://docs.u-boot.org/en/latest/develop/codingstyle.html#include-files Reviewed-by: Patrick Delaunay Signed-off-by: Patrice Chotard